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Observer
Observer
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Registered: ‎10-08-2009

Generating a synthesizable netlist in Viavdo

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How do I create a synthesizable netlist from VHDL code so I can give this to a customer and he can't read / modify my VHDL code?

 

Maybe I don't mean synthesizable netlist, a block box netlist that can be inserted into another design, just a way so the VHDL code can't be read / modified.

 

I know how to do this in ISE with an NGC file but not sure in Vivado. write_vhdl apparently is for simulation only?

 

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Moderator
Moderator
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Registered: ‎06-24-2015

Re: Generating a synthesizable netlist in Viavdo

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Hi luis.munoz,

Yes write_vhdl is for simulation netlist file also, but can be used for synthesized netlist too. You can use the write_edif command instead.

After the synthesis of the required module is done in out of context mode, write this command in tcl console:

write_vhdl -mode synth_stub .v

Then write this command in tcl console:

write_edif -security_mode all -force .edn

Now you can simply add the netlist and instantiate it in your project just like any other module

 

Refer to this document for details on syntax:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_4/ug835-vivado-tcl-commands.pdf

 

Regarding black box requirement: You can simply use black_box attribute in Vivado. Refer below link(page 39):

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_4/ug901-vivado-synthesis.pdf

 

Thanks,
Nupur

Thanks,
Nupur
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Moderator
Moderator
19,415 Views
Registered: ‎06-24-2015

Re: Generating a synthesizable netlist in Viavdo

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Hi luis.munoz,

Yes write_vhdl is for simulation netlist file also, but can be used for synthesized netlist too. You can use the write_edif command instead.

After the synthesis of the required module is done in out of context mode, write this command in tcl console:

write_vhdl -mode synth_stub .v

Then write this command in tcl console:

write_edif -security_mode all -force .edn

Now you can simply add the netlist and instantiate it in your project just like any other module

 

Refer to this document for details on syntax:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_4/ug835-vivado-tcl-commands.pdf

 

Regarding black box requirement: You can simply use black_box attribute in Vivado. Refer below link(page 39):

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_4/ug901-vivado-synthesis.pdf

 

Thanks,
Nupur

Thanks,
Nupur
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (click on the 'thumbs-up' button).

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Observer
Observer
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Registered: ‎04-09-2013

Re: Generating a synthesizable netlist in Viavdo

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Hi nupurs,

 

I have a similar scenario and a question: I only have a part of my design encrypted. And, when I do write_edif, that part gets separated into a second .edn-file, in accordance with the default security_mode setting, which is multifile.

 

Now my client gets the top-.edf-file and the encrypted .edn-file. He added both to a new project, but the encrypted .edn-file is not used during synthesis. He gets a critical warning:

 

[Project 1-486] Could not resolve non-primitive black box cell <name of encrypted vhdl module> instantiated as ...

 

I know I could just change the security_mode and get a single file as output, but I was curious if you knew how to deal with importing multiple netlist-files.

 

Thanks a lot,

Andrei

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Adventurer
Adventurer
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Registered: ‎08-21-2016

Re: Generating a synthesizable netlist in Viavdo

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@luis.munoz hi,
 
I am working on zynq7020 customized board, I have created the complete video pipeline part in PL side . now I have to give this to my customer , my customer need to add some more logic into PL Side, But I cant directly give my PL block Design to them. when I am searching someone posted about the NETLIST, from that they extract the design and  add their logic into PL side. could u please explain WHAT and HOW can I generate my complete PL DESIGN NETLIST. if u have done this before could u please explain me.. u can contact me @ ramesha15390@gmail.com
 
WITH REGARDS
RAMESH
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Moderator
Moderator
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Registered: ‎07-21-2014

Re: Generating a synthesizable netlist in Viavdo

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@theertharamesha

 

You can shared the synthesized netlist in the form of .edf of .dcp by using write_edif/write_checkpoint command after synthesis. Your customer needs to instantiate this file in the design with the other logic.

 

Thanks,
Anusheel
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Adventurer
Adventurer
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Registered: ‎08-21-2016

Re: Generating a synthesizable netlist in Viavdo

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thank you @anusheel,

I have generated the synthesized netlist with tcl command. now I want to test these netlist file whatever I have generated is correct?
for that I need to create a sample project with some logic and for that I need to instantiate my netlist. could you please tell how can I instantiate my netlist .
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Moderator
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Registered: ‎07-21-2014

Re: Generating a synthesizable netlist in Viavdo

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@theertharamesha 

 

You will need to have a stub for this flow. Please refer below AR:

https://www.xilinx.com/support/answers/54074.html

Thanks,
Anusheel
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Adventurer
Adventurer
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Registered: ‎08-21-2016

Re: Generating a synthesizable netlist in Viavdo

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thank you @anusheel,

I have followed the steps u have been mentioned . I have instantiated the .edf & Verilog stub file in my main design . but I am getting implementation error.

 

please look into the snap chat of the error message

 

 

with regards

ramesh

block_box.jpg
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