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Visitor david107
Visitor
5,743 Views
Registered: ‎02-07-2012

HELP ME....bad synchronous description

I have this code in my description.....

 

proc0 : process(c5_load,c6_shift) is
variable buff :STD_LOGIC_VECTOR (7 downto 0):="00000000" ;
begin


if (c5_load = '1' and c5_load'event) then
buff:= ADDER_EXIT;
OUTPUT_A<=buff;	


elsif (c6_shift ='1' and c6_shift'event) then
A0 <= buff(0);
buff := buff(7) & buff(7 downto 1);
OUTPUT_A<=buff;	

end if;
	
end process proc0;

 but there is an error:

 

Signal buff cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

 

WHY?

 

Thanks so much

 

 

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5 Replies
Teacher eteam00
Teacher
5,735 Views
Registered: ‎07-21-2009

Re: HELP ME....bad synchronous description

Aside from the use of two different clocks for a single register -- c5_load and c6_shift -- not much to worry about.  Which FPGA family has more than one clock per register?

 

The use of blocking and non-blocking assignments in a clocked process is a bit sloppy.

You should ask your VHDL course instructor to give you a helping hand.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Historian
Historian
5,731 Views
Registered: ‎02-25-2008

Re: HELP ME....bad synchronous description


@david107 wrote:

I have this code in my description.....

 

proc0 : process(c5_load,c6_shift) is
variable buff :STD_LOGIC_VECTOR (7 downto 0):="00000000" ;
begin


if (c5_load = '1' and c5_load'event) then
buff:= ADDER_EXIT;
OUTPUT_A<=buff;	


elsif (c6_shift ='1' and c6_shift'event) then
A0 <= buff(0);
buff := buff(7) & buff(7 downto 1);
OUTPUT_A<=buff;	

end if;
	
end process proc0;

 but there is an error:

 

Signal buff cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.

 

WHY?

 

Thanks so much

 

 


Yup, that's a bad synchronous description!
You should read the XST user guide to see what the tool expects.

----------------------------Yes, I do this for a living.
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Visitor david107
Visitor
5,717 Views
Registered: ‎02-07-2012

Re: HELP ME....bad synchronous description

c5_load,c6_shift are two signals in input that come from my control unit.....
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Teacher eteam00
Teacher
5,708 Views
Registered: ‎07-21-2009

Re: HELP ME....bad synchronous description

c5_load,c6_shift are two signals in input that come from my control unit...

 

Does your control unit have a clock?

If so, will your control unit mind sharing its clock with the rest of your design?

 

Have you figured out the answer to this question: Which FPGA family has more than one clock per register?

Do you understand why I ask this question?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Xilinx Employee
Xilinx Employee
5,703 Views
Registered: ‎10-12-2011

Re: HELP ME....bad synchronous description

All the above comments are very valid.

 

If c5_load & c6_shift are two separate clocks in to this module it would be preferrable to split the single big process into two processes and if your code allows replace variable to signal declaration on the buff.

 

-Hari

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