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Newbie jj_gonzalez
Newbie
352 Views
Registered: ‎07-24-2019

Help decreasing LUTs usage.

Hi.

When I try to implement my desing, appears next: 

  • [Place 30-487] The packing of instances into the device could not be obeyed. There are a total of 13300 slices in the device, of which 3457 slices are available, however, the unplaced instances require 3622 slices. Please analyze your design to determine if the number of LUTs, FFs, and/or control sets can be reduced. Number of control sets and instances constrained to the design Control sets: 709 Luts: 46343 (combined) 56925 (total), available capacity: 53200 Flip flops: 10687, available capacity: 106400 NOTE: each slice can only accommodate 1 unique control set so FFs cannot be packed to fully fill every slice

In synthesis view, I see that LUTs usage is about 94%, and I think that is my problem. I am trying to reduce these number. About this 94%, I have been able to find out that 70% is the fault of a mathematical operation that I do many times, and it is a mapping function. I have attached two files (hey belong to an IP block that I have repeated many times), where I do the operation that I have mentioned.

Hope you can help me!

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10 Replies
Scholar drjohnsmith
Scholar
338 Views
Registered: ‎07-09-2009

Re: Help decreasing LUTs usage.

why you using std_logic_unsigned ?

if its a PWM , where is the clock ?

 

 

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Newbie jj_gonzalez
Newbie
334 Views
Registered: ‎07-24-2019

Re: Help decreasing LUTs usage.

It is a PWM which has been sampler before this block into std_logic_vector.

I upload the file again since I had added a variable to do a test.

 

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Newbie jj_gonzalez
Newbie
326 Views
Registered: ‎07-24-2019

Re: Help decreasing LUTs usage.

To give you an idea, by removing the mathematical operation in pwm_map1, I reduce the use of LTUs by 70%

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Adventurer
Adventurer
319 Views
Registered: ‎06-25-2014

Re: Help decreasing LUTs usage.

Your file is all combinational so I have no idea of what timing you require.

All I can suggest is instead of adding multiple instances of this file as it stands is to modify it where a single instance is capable of processing multiple results. For example if you need a result wihin 100nS then you could clock your algorithm at 100MHz and sequence 10 calculations through it. This would then reduce your logic to 1/10th of the current size.

 

 

Newbie jj_gonzalez
Newbie
303 Views
Registered: ‎07-24-2019

Re: Help decreasing LUTs usage.

My problem, right now, isn't with timing, it is about the number of LTUs used to implement the function to obtain the mapped number (pwm_map1). Removing this function, the LTUs usage is 17%. Any advice to change this function (line 80 of PWM_Manager_Core.vhd)?

 

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Scholar drjohnsmith
Scholar
283 Views
Registered: ‎07-09-2009

Re: Help decreasing LUTs usage.

yes,

 

clock the process,

     then over smaple.

 

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Adventurer
Adventurer
270 Views
Registered: ‎06-25-2014

Re: Help decreasing LUTs usage.

You cannot throw an algorithm like that at an FPGA without some thought. Your current file looks like a direct conversion into the vhdl language from a 'C' function.

FPGA design revolves around the usage of clocks. Seeing a file that is all combinational (particularly a file where it's doing an algorithm of a whole series of mults/divisions/Muxes etc.) sets off warning bells. And yes, I’m sure line 80 is the bulk of your LUT usage.

 

You need to introduce a clock into your design, you need to use that to break up your algorithm into steps using clocked registers, you need to consider logic reuse which is what I was describing above. This is how you will reduce your LUT usage.

 

Or, you could just reduce your bus widths (and dynamic range) by 50% which will reduce logic usage by 50% and stick with being all combinational if that’s what you really want.. 

Newbie jj_gonzalez
Newbie
233 Views
Registered: ‎07-24-2019

Re: Help decreasing LUTs usage.

Thank you very much. Yes, I am a c/c++ programmer and I an a newbie with FPGAs. I will think about how to introduce a clock into the system and do it as you tell me. Any advice?

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Scholar drjohnsmith
Scholar
218 Views
Registered: ‎07-09-2009

Re: Help decreasing LUTs usage.

Advice...

a) forget programming languages, RTL is a hardware description language,

b) programming assumes a single processor, running fats, FPGAs get there speed by massive parallel and pipe lining

c) First understand  what hardware / logic you want , then code to produce it.

 

 

Most important,  ......     Get a good book on FPGAs / VHDL ....  and go through the examples your self.

 

 

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Adventurer
Adventurer
204 Views
Registered: ‎06-25-2014

Re: Help decreasing LUTs usage.

The only other advice I can offer other than DrJohnSmith's above is that you also consider using Vivado HLS which is basically a C/C++ to gates tool. There are loads of documents covering the subject available here and also a separate area on the Xilinx forums dedicated to HLS. 

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