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Visitor huangpoh
Visitor
2,485 Views
Registered: ‎07-20-2017

Help identifying VHDL Signal forming Combinatorial Loop

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Hi Everyone,

 

Can someone help me identify a the Combinatorial Loop for my simple FSM?

 

I get this warning : Unit FSM4 : the following signal(s) form a combinatorial loop: Z1. when I sythesize 

 

architecture Behavioral of FSM4 is

type STATE is (ST0,ST1);
signal CURRENT_STATE : STATE := ST0 ;
signal NEXT_STATE : STATE;

begin

	process (CLR, NEXT_STATE) is
	begin
		if (CLR = '1') then
			CURRENT_STATE <= ST0;
		else
			CURRENT_STATE <= NEXT_STATE;
		end if;
	
	end process;
	
	process(CURRENT_STATE,TOG_EN) is
	begin
		Z1<='0';
		case (CURRENT_STATE) is
		 when ST0 => 
			Z1 <= '0';
			if(TOG_EN = '1') then 
			NEXT_STATE <= ST1;
			else 
			NEXT_STATE <= ST0;
			end if;
		 when ST1 =>
		   Z1 <= '1';
			if(TOG_EN = '1')then
			NEXT_STATE <= ST0;
			else
			NEXT_STATE <= ST1;
			end if;
		 when others =>
			Z1 <= '0';
		   NEXT_STATE <= ST0;
			
		end case;
	
	end process;

end Behavioral;

However If I sythesize this code everything is OK, the only difference I see is that the below code has a Clock and the above one doesn't. 

 

architecture Behavioral of FSM is
	type STATE_TYPE is (ST0,ST1);
	signal CURRENT_STATE : STATE_TYPE := ST0;
	signal NEXT_STATE : STATE_TYPE;
	
begin
	
	process (CLR,CLK,NEXT_STATE) is
	begin
		
		if (CLR = '1') then
			CURRENT_STATE <= ST0;
		elsif (rising_edge(CLK)) then 
			CURRENT_STATE <= NEXT_STATE;
		end if ;
	
	end process;

	process(CURRENT_STATE,TOG_EN) is
	begin
		Z1<='0';
		case (CURRENT_STATE) is
		 when ST0 => 
			Z1 <= '0';
			if(TOG_EN = '1') then 
			NEXT_STATE <= ST1;
			else 
			NEXT_STATE <= ST0;
			end if;
		 when ST1 =>
		   Z1 <= '1';
			if(TOG_EN = '1')then
			NEXT_STATE <= ST0;
			else
			NEXT_STATE <= ST1;
			end if;
		 when others =>
			Z1 <= '0';
		   NEXT_STATE <= ST0;
			
		end case;
	
	end process;

	with CURRENT_STATE select
		Y <= '1' when ST1 ,
			  '0' when ST0 ,
			  '0' when others;


end Behavioral;

In all the examples I've ran into all has the FSM has a clock, I was trying to create one that does not have a CLK

 

Thanks in advance

Po

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1 Solution

Accepted Solutions
Scholar u4223374
Scholar
4,046 Views
Registered: ‎04-26-2015

Re: Help identifying VHDL Signal forming Combinatorial Loop

Jump to solution

Think about what happens when CLR=0 and TOG=1.

 

At time 0: CURRENT_STATE is ST0, so NEXT_STATE = ST1
At time 0: CURRENT_STATE = NEXT_STATE = ST1
At time 0: CURRENT_STATE is ST1, so NEXT_STATE = ST0
At time 0: CURRENT_STATE = NEXT_STATE = ST0 
At time 0: CURRENT_STATE is ST0, so NEXT_STATE = ST1
At time 0: CURRENT_STATE = NEXT_STATE = ST1
At time 0: CURRENT_STATE is ST1, so NEXT_STATE = ST0
At time 0: CURRENT_STATE = NEXT_STATE = ST0 
At time 0: CURRENT_STATE is ST0, so NEXT_STATE = ST1
At time 0: CURRENT_STATE = NEXT_STATE = ST1
At time 0: CURRENT_STATE is ST1, so NEXT_STATE = ST0
At time 0: CURRENT_STATE = NEXT_STATE = ST0 
At time 0: CURRENT_STATE is ST0, so NEXT_STATE = ST1
At time 0: CURRENT_STATE = NEXT_STATE = ST1
At time 0: CURRENT_STATE is ST1, so NEXT_STATE = ST0
At time 0: CURRENT_STATE = NEXT_STATE = ST0 
At time 0: CURRENT_STATE is ST0, so NEXT_STATE = ST1
At time 0: CURRENT_STATE = NEXT_STATE = ST1
At time 0: CURRENT_STATE is ST1, so NEXT_STATE = ST0
At time 0: CURRENT_STATE = NEXT_STATE = ST0 
At time 0: CURRENT_STATE is ST0, so NEXT_STATE = ST1
At time 0: CURRENT_STATE = NEXT_STATE = ST1
At time 0: CURRENT_STATE is ST1, so NEXT_STATE = ST0
At time 0: CURRENT_STATE = NEXT_STATE = ST0 
At time 0: CURRENT_STATE is ST0, so NEXT_STATE = ST1
At time 0: CURRENT_STATE = NEXT_STATE = ST1
At time 0: CURRENT_STATE is ST1, so NEXT_STATE = ST0
At time 0: CURRENT_STATE = NEXT_STATE = ST0 
.. and so on

In this situation, what result are you expecting the tools to produce? There is no stable state for the system that your code describes.

 

In contrast, the clocked one does the following:

At time 0: CURRENT_STATE is ST0, so NEXT_STATE = ST1

At time 1: CURRENT_STATE = NEXT_STATE = ST1
At time 1: CURRENT_STATE is ST1, so NEXT_STATE = ST0

At time 2: CURRENT_STATE = NEXT_STATE = ST0 
At time 2: CURRENT_STATE is ST0, so NEXT_STATE = ST1

At time 3: CURRENT_STATE = NEXT_STATE = ST1
At time 3: CURRENT_STATE is ST1, so NEXT_STATE = ST0

At time 4: CURRENT_STATE = NEXT_STATE = ST0 
At time 4: CURRENT_STATE is ST0, so NEXT_STATE = ST1

At time 5: CURRENT_STATE = NEXT_STATE = ST1
At time 5: CURRENT_STATE is ST1, so NEXT_STATE = ST0

.. and so on

At each time period (defined by the clock) there is a stable state. The system gets into that state and stays there.

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5 Replies
Highlighted
Historian
Historian
2,479 Views
Registered: ‎01-23-2009

Re: Help identifying VHDL Signal forming Combinatorial Loop

Jump to solution

In all the examples I've ran into all has the FSM has a clock, I was trying to create one that does not have a CLK

 

By definition, a finite state machine without a clock (if you can even call it an FSM) is a combinational loop - it can't be anything else. The "state" has to be combinatorially reinforced by the combinatorial loop (since there are no memory elements).

 

While asynchronous state machines can exist, nobody uses them in real designs and especially not in FPGAs. The entire tool chain is designed to work with synchronous design techniques - this is absolutely not one.

 

I don't know what you are trying to accomplish. If it is anything "real" (i.e. other than an academic exercise to try and implement an asynchronous state machine), this is not the way to do it.

 

Avrum

Tags (2)
Teacher muzaffer
Teacher
2,461 Views
Registered: ‎03-31-2012

Re: Help identifying VHDL Signal forming Combinatorial Loop

Jump to solution

@huangpoh

 

>> In all the examples I've ran into all has the FSM has a clock

 

because there is a very good reason for it. The alternative of having storage which doesn't need a clock is extremely difficult to get right so almost all designs use one and most tools support only clocked designs.

 

Why do you want to have a design with no clock anyway? 

- Please mark the Answer as "Accept as solution" if information provided is helpful.
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Scholar u4223374
Scholar
4,047 Views
Registered: ‎04-26-2015

Re: Help identifying VHDL Signal forming Combinatorial Loop

Jump to solution

Think about what happens when CLR=0 and TOG=1.

 

At time 0: CURRENT_STATE is ST0, so NEXT_STATE = ST1
At time 0: CURRENT_STATE = NEXT_STATE = ST1
At time 0: CURRENT_STATE is ST1, so NEXT_STATE = ST0
At time 0: CURRENT_STATE = NEXT_STATE = ST0 
At time 0: CURRENT_STATE is ST0, so NEXT_STATE = ST1
At time 0: CURRENT_STATE = NEXT_STATE = ST1
At time 0: CURRENT_STATE is ST1, so NEXT_STATE = ST0
At time 0: CURRENT_STATE = NEXT_STATE = ST0 
At time 0: CURRENT_STATE is ST0, so NEXT_STATE = ST1
At time 0: CURRENT_STATE = NEXT_STATE = ST1
At time 0: CURRENT_STATE is ST1, so NEXT_STATE = ST0
At time 0: CURRENT_STATE = NEXT_STATE = ST0 
At time 0: CURRENT_STATE is ST0, so NEXT_STATE = ST1
At time 0: CURRENT_STATE = NEXT_STATE = ST1
At time 0: CURRENT_STATE is ST1, so NEXT_STATE = ST0
At time 0: CURRENT_STATE = NEXT_STATE = ST0 
At time 0: CURRENT_STATE is ST0, so NEXT_STATE = ST1
At time 0: CURRENT_STATE = NEXT_STATE = ST1
At time 0: CURRENT_STATE is ST1, so NEXT_STATE = ST0
At time 0: CURRENT_STATE = NEXT_STATE = ST0 
At time 0: CURRENT_STATE is ST0, so NEXT_STATE = ST1
At time 0: CURRENT_STATE = NEXT_STATE = ST1
At time 0: CURRENT_STATE is ST1, so NEXT_STATE = ST0
At time 0: CURRENT_STATE = NEXT_STATE = ST0 
At time 0: CURRENT_STATE is ST0, so NEXT_STATE = ST1
At time 0: CURRENT_STATE = NEXT_STATE = ST1
At time 0: CURRENT_STATE is ST1, so NEXT_STATE = ST0
At time 0: CURRENT_STATE = NEXT_STATE = ST0 
.. and so on

In this situation, what result are you expecting the tools to produce? There is no stable state for the system that your code describes.

 

In contrast, the clocked one does the following:

At time 0: CURRENT_STATE is ST0, so NEXT_STATE = ST1

At time 1: CURRENT_STATE = NEXT_STATE = ST1
At time 1: CURRENT_STATE is ST1, so NEXT_STATE = ST0

At time 2: CURRENT_STATE = NEXT_STATE = ST0 
At time 2: CURRENT_STATE is ST0, so NEXT_STATE = ST1

At time 3: CURRENT_STATE = NEXT_STATE = ST1
At time 3: CURRENT_STATE is ST1, so NEXT_STATE = ST0

At time 4: CURRENT_STATE = NEXT_STATE = ST0 
At time 4: CURRENT_STATE is ST0, so NEXT_STATE = ST1

At time 5: CURRENT_STATE = NEXT_STATE = ST1
At time 5: CURRENT_STATE is ST1, so NEXT_STATE = ST0

.. and so on

At each time period (defined by the clock) there is a stable state. The system gets into that state and stays there.

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Visitor huangpoh
Visitor
2,268 Views
Registered: ‎07-20-2017

Re: Help identifying VHDL Signal forming Combinatorial Loop

Jump to solution

The reason that I was wondering if it is possible, in my design there is a XC9500XL CPLD without external clock, in the datasheet I don't see an internal clock so I was wondering how I would go about creating a FSM without a clock, are there CPLDs or FPGAs with internal clocks?

 

I think I just answered my question there is no internal clock for CPLDs, however there are PLLs clock synthesis blocks in FPGAs however you would still need a source from an external clock, or https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf 

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Teacher muzaffer
Teacher
2,264 Views
Registered: ‎03-31-2012

Re: Help identifying VHDL Signal forming Combinatorial Loop

Jump to solution

@huangpoh CPLDs are a lot more deterministic in terms of timing so  I think it would be possible to create an internal oscillator which can be controlled enough to have a period which is always useful to use inside the chip. You wouldn't be able to control the exact period but the range so that you can check setup timing.

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