cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
jptalledo
Visitor
Visitor
2,924 Views
Registered: ‎12-04-2009

Help with 2677 Error : Node XX of sequential type is uinconnected in block XX

I am getting a lot of 2677 errors for my char_buffer register.  if I comment the line:

 

assign sample_out = char_buffer; I don't receive any complains but I need to wire the char_buffer register to this output.

 

char_buffer get serial data from SPI.

 

 

My code is here:

 

 

module ext_ADC( CS, SCLK, sample_out, sample_update, SDATA, start, clock, reset);
 
  output  CS;   //Chip Select
  output  SCLK;   //Output clock to the ADC
  output [11:0] sample_out; //Current ADC Sample
  output  sample_update;   //flag for ready data

  input  SDATA;  //Serial data out from the ADC
  input  start;  //Start
  input clock;  //System clock
  input reset;   //System Reset
 
  localparam  IDLE_STATE  = 2'd0,  //State variables
      START_ADC = 2'd1,
      RUN_ADC  = 2'd2,
      PAUSE_ADC = 2'd3;
 
 assign SCLK = ~clock;  //Inverse of clock used to drive the ADC
 
 reg [1:0]  state = IDLE_STATE;    //State Machine variable
 reg [4:0]  ad_counter;                 //Counter used for ADC
 
 reg adc_conv;
 reg [11:0] char_buffer;
   reg [4:0]  bit_counter;

    reg start_bit;
    reg  update;
  reg prev_CS;
 


 assign sample_out= char_buffer[11:0];
 assign sample_update = update;
 
 
 
 
 
 //ADC Control Bits
 assign ad_start = (ad_counter == 6'd0) && (state == START_ADC);
 assign ad_data  = (ad_counter >= 6'd1) && (ad_counter <= 6'd15);
 
 assign CS = adc_conv;
 
 
 always @(posedge clock or posedge reset) begin
      if (reset) begin
   start_bit <=0;
         bit_counter <= 5'b00000;
   prev_CS <=0;
   end
  else begin
  
    if (prev_CS ==0 && adc_conv==1)
    start_bit <=1;
    else
    start_bit <=0;
   
   
    if (start_bit) begin
    bit_counter <= bit_counter+1;
   
    if (bit_counter==15) begin
     start_bit<= 0;
     bit_counter <= 0;
    end
    
    
         end
   prev_CS <= adc_conv;
  
 
  end
    end  

 

 always @(posedge clock or posedge reset) begin
      if (reset) begin
   char_buffer <= 12'd0;
   
   end
  else begin
   if (bit_counter >= 6'd3 || bit_counter <= 6'd16)
            char_buffer <= {char_buffer[10:0], SDATA};
    else
    char_buffer <= char_buffer;
    
    end
 end

   
   
   
 
 //AD Counter, increments the bit counter by 1 each clock cycle
    always @(posedge clock or posedge reset) begin
   if (reset)
     ad_counter <= 6'd0;
   else begin
    if (ad_start || ad_data)    //*************
     ad_counter <= ad_counter + 6'd1;
    else
     ad_counter <= 6'd0;
   end
    end  
 
 always @(posedge clock or posedge reset) begin
  if(reset)
   adc_conv<= 1'd1;
  else begin
   if(state == START_ADC) begin
    adc_conv <= 1'd0;
   end else if(state == PAUSE_ADC) begin
    adc_conv <= 1'd1;
   end
  end
 end
   
 //State Machine
 always @(posedge clock or posedge reset) begin
  if(reset) 
   state <= IDLE_STATE;
  else begin   
   case(state)
    IDLE_STATE:
     if(start == 1'b1)
      state <= START_ADC;
     else
        state <= IDLE_STATE;
    START_ADC:
     state <= RUN_ADC;
    RUN_ADC:
     if(ad_counter == 6'd15)  
      state <= PAUSE_ADC;
    PAUSE_ADC:
     state <= START_ADC;
    default:
     state <= IDLE_STATE;
   endcase
  end
 end
 
 

endmodule

0 Kudos
1 Reply
gszakacs
Professor
Professor
2,919 Views
Registered: ‎08-14-2007

I tried this code and the only thing I see is that signal "update" is not

driven anywhere, so sample_update will be tied to zero.  However I don't

see the errors you report on sample_out.  Did you try to clean up your

project files and re-run synthesis?

-- Gabor
0 Kudos