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khyu
Contributor
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Registered: ‎10-28-2018

How can I check the floating input or undriver net

How can I check floating input signal or undriver net.

I have one signal usbcpurdy that is floating. But the vivado synthesis connect the floating signal to ground and no any message.

How can I check the floating signal by vivado

 

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seamusbleu
Voyager
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Registered: ‎08-12-2008

I suggest you give more information about your problem.  What is your code?  What makes you think that Vivado connected "the floating signal" to ground?  Do you mean the signal is an input to the FPGA, and external to the FPGA it's floating? 

Synthesis won't connect an input to ground, and it doesn't know if a signal is floating.  You could open the synthesized design and look for the signal in the schematic - maybe that will give you some ideas what is happening.

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drjohnsmith
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Registered: ‎07-09-2009

My old mantra #2

whats the simulation look like ?

 

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khyu
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Registered: ‎10-28-2018

Hi Seamusbleu :

The input pin usbcpurdy of module cputop is n/c , no connect  because I miss to assign the value to this usbcpurdy pin

 

khyu_0-1627260661935.png

But after synthesis , the usbcpurdy pin is connected to ground

 

 

khyu_1-1627260940051.png

 

 

 

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drjohnsmith
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Registered: ‎07-09-2009

IP modules often have a default level for input pins, 

    saves having to wire up everything,

    So I would suggest the default for this pin in the IP is "gnd" 

 

It should be mentioned in the data sheet for the IP what the default level is for any input that  has it defined. 

 

Now, in a "proper" language like VHDL ,

   the designer puts open on pins they don't want to use, so the compiler can find this mistake, 

      But Xilxin does not seem to support that....

       but that's another discussion  

 

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dpaul24
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Registered: ‎08-07-2014

@khyu ,

How can I check floating input signal or undriver net.

The best way..............perform functional verification via simulation! Please follow all the design methodology steps to avoid future problems in design (like the one you are having).

Do you have a testbench exercising your DUT?

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khyu
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Registered: ‎10-28-2018

Hi drjohnsmith:

? ? ? ? ? ?The our module "cputop" is not IP. The cputop is my design and is written by verilog .

So I don''t set any default value of input in module cputop.

Now I check the floating input pins by Synopsys SPYGLASS lint.

But If the xilinx vivado can report the floating input pins , it is better and?convenient

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khyu
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Registered: ‎10-28-2018

Hi drjohnsmith:

? ? ? ? ? ?The our module "cputop" is not IP. The cputop is my design and is written by verilog .

So I don''t set any default value of input in module cputop.

Now I check the floating input pins by Synopsys SPYGLASS lint.

But If the xilinx vivado can report the floating input pins , it is better and?convenient

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dpaul24
Scholar
Scholar
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Registered: ‎08-07-2014

@khyu ,

Seems like you are doing some ASIC prototyping task (speculating as Linting tools are less frequently used in a FPGA based design flow)? Now there is a difference how ASIC frontend engineers debug/improve their designs compared to FPGA design engineers.

In my case, I do not have a variety of tools available. So I make sure my design has the least possible ambiguity right from the start. In order to do so I take care about....

1. Robust RTL coding methodology

2. Functional verification via simulation and improving the design by simulation iterations (as needed) before Synthesis.

3. Supply a properly constrained design (exact as much as possible) to the Synthesis tool and checking the synthesis log thereafter.

4. Implementation

Now I as I see your case, I see that step <2> is missing. Also did you check the Synthesis log in details?

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khyu
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Registered: ‎10-28-2018

Hi dpaul24

                 I don't get any message about signal "usbcpurdy" in Synthesis log.

But I got another message 

WARNING: [Synth 8-3295] tying undriven pin u10_ae250:X_trst to constant 0

 

But I have assigned value to X_trst but the X_trst is not used in our design .

X_trst is unused signal but not undriven signal

 

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seamusbleu
Voyager
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Registered: ‎08-12-2008

You usbcpurdy signal is not a input to the FPGA, it's an input to a module in your FPGA design - that wasn't apparent at first.  You haven't given us any indication of how, or if, that signal is used in cputop, but I'm guessing it's used in a logic equation.  And in the anything goes world of verilog, it'll give that signal a value of '0' if you don't give it any value.  As @drjohnsmith said, in VHDL, it would get flagged as an error.  In verilog, I don't think that's even considered a warning, though some lint tools will pick that up for you.  As has been said previously, simulation would also be another way to discover that the signal is undriven.

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