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Explorer
Explorer
8,663 Views
Registered: ‎11-02-2011

How can I know my state machine is encoded?

Hi All,

 

  If -fsm_extraction is set to auto, after synthesis, how can I know my state machine is encoded?

 

Thanks

Rgds

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7 Replies
Xilinx Employee
Xilinx Employee
8,659 Views
Registered: ‎09-20-2012

Re: How can I know my state machine is encoded?

Hi,

 

You can check the synthesis log file which gives these details. Below are the messages which gives this info. In this case it used sequential encoding.

 

---------------------------------------------------------------------------------

Finished RTL Optimization : Time (s): cpu = 00:00:04 ; elapsed = 00:00:10 . Memory (MB): peak = 260.242 ; gain = 113.801
---------------------------------------------------------------------------------

INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'fsm_test'
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'fsm_test'

 

Thanks,

Deepika.

Thanks,
Deepika.
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Xilinx Employee
Xilinx Employee
8,652 Views
Registered: ‎05-14-2008

Re: How can I know my state machine is encoded?

I believe you're using Vivado. In Vivado 2013.3, for verilog we do provide encoding values for each state in the report file. Here is a snippet,
INFO: [Synth 8-638] synthesizing module 'fsm_test' [....]
Parameter s1 bound to: 2'b00

 

For VHDL even in 2013.3, we do not provide the values in the report file. For debugging perspective from synthesis side, one suggestion for a workaround would be to explicitly specify encoding value in a combinatorial process for a specific state,synthesize and using it for debugging. The sample HDL code is as follows,

process(state) begin
case state is
when s1 => test_out <= "00";
when s2 => test_out <= "01";
end case;
end process;

test_out can be used for debugging purpose.

 

 

In the future release of Vivado, more accurate messages about FSM state encoding will be added into Synthesis report but we don't have a fixed schedule yet.

 

Thanks

Vivian

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Historian
Historian
8,631 Views
Registered: ‎02-25-2008

Re: How can I know my state machine is encoded?


@viviany wrote:

I believe you're using Vivado. In Vivado 2013.3, for verilog we do provide encoding values for each state in the report file. 


Just for the record, the XST report shows the encoding type and exactly how each state is encoded. It has done so basically since the tool was first released.

----------------------------Yes, I do this for a living.
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Explorer
Explorer
8,609 Views
Registered: ‎11-02-2011

Re: How can I know my state machine is encoded?

Thank you all. Got it.

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5,613 Views
Registered: ‎04-10-2012

Re: How can I know my state machine is encoded?

The old technique used in ISE seems to be accepted in vivado 14.3:

In synthesis report:

   INFO: [Synth 8-4472] Detected and applied attribute fsm_encoding = user

 

and in chipscope the values for the fsm signal have always been as i set in attributes using

   type myStateType                              is ( STATE1, STATE2 );

   attribute ENUM_ENCODING of myStateType : type is " 000            001        ";


   signal myState          : myStateType := STATE1;
   attribute FSM_ENCODING        of myState : signal is "user";
   attribute SAFE_IMPLEMENTATION of myState : signal is "yes";

 

all this does not exist in Vivado doc... am i day dreaming or the Vivado synthesiser is still accepting them (undocumented features?)

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Moderator
Moderator
5,596 Views
Registered: ‎07-21-2014

Re: How can I know my state machine is encoded?

@fjeanson_eddyfi

 

Refer below link:

http://www.xilinx.com/support/answers/51237.html

 

Thanks,
Anusheel
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5,537 Views
Registered: ‎04-10-2012

Re: How can I know my state machine is encoded?

In Vivado 2014.4 and older versions, Vivado Synthesis does not support "user_encoding" for the fsm_encoding attribute.
Support for "user_encoding" is added in Vivado 2015.1

ref:

http://www.xilinx.com/support/answers/60916.html

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