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Explorer
Explorer
1,679 Views
Registered: ‎01-23-2018

[How can it be possible?]

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Hello,

 

I have a module that is called from 2 different files with different value in the parameters (width and depth), this parameters creates an array inside the module, the code is simple but I can't share it due to confidentiality. It doesn't have any iteration loop inside, just some if/else. Both instantiation uses similar values:

 

  • The first file instantiates the module one time -->  width = 600 depth = 2
  • The second file uses a generate loop that uses the same parameters in all iterations, this loop create X instantiations where everyone have this values --> width = 550 depth = 2

 

When I do the synthesis the first file instantiation uses 38344 cells and the second one 3430 for each instantiation. How can it be possible with parameters without much difference?

 

Both values are seen in section Report Instance Areas section on the logfile.

 

Any idea of what is happening or how can I solve it? I have other calls to the module and it has normal values like the second file instantiations.

 

 

Thanks. 

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Moderator
Moderator
1,926 Views
Registered: ‎07-21-2014

Re: [How can it be possible?]

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@joel.sanchez

 

One simple check that you can perform is: Apply DONT_TOUCH in the module where "generate" block is used and this will stop any optimizations(if any).

 

Thanks,

Anusheel

14 Replies
Scholar jmcclusk
Scholar
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Registered: ‎02-24-2014

Re: [How can it be possible?]

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Try isolating this synthesis into separate compiles, and examine the results again.  It sounds like there's some confusion between the instances.   you can do this pretty easily by going down into the source hierarchy, and right clicking on a module and selecting "Set as Top".    Then run the synthesis again with this new top module..    This may not work if you don't have default values for generic parameter in the new top module.

Don't forget to close a thread when possible by accepting a post as a solution.
Scholar markcurry
Scholar
1,665 Views
Registered: ‎09-16-2009

Re: [How can it be possible?]

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Another thing to consider - what is your metric: "cells" doesn't mean much in an FPGA.

LUTs, BRAMs, and Distribute RAMs should be your metrics.  i.e. "report_utilization"

 

You mention arrays - could one instance be inferring BRAMs, but the other LUTs? (For whatever reason).

 

Regards,

 

Mark

Scholar markcurry
Scholar
1,659 Views
Registered: ‎09-16-2009

Re: [How can it be possible?]

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One other possibility - is the logic from both sets of instances fully functional and actual used in real way?  If synthesis decides either of the instances has tied off inputs, or outputs that are unused - it'll optimize your logic down to about nothing.

 

Are you synthesizing a full design, or just some sub-modules?  If the latter, did you specify OOC synthesis?

 

Regards,

Mark

Explorer
Explorer
1,599 Views
Registered: ‎01-23-2018

Re: [How can it be possible?]

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Hi @jmcclusk and @markcurry,

 

first of all thanks for helping.

 

Try isolating this synthesis into separate compiles, and examine the results again.  It sounds like there's some confusion between the instances.   you can do this pretty easily by going down into the source hierarchy, and right clicking on a module and selecting "Set as Top".    Then run the synthesis again with this new top module..    This may not work if you don't have default values for generic parameter in the new top module.

I would try this and reply as soon as possible, I have all parameters with default values so it won't be any problem.

 

You mention arrays - could one instance be inferring BRAMs, but the other LUTs? (For whatever reason).

I have enough BRAM and both arrays have pretty the same size so if it put one of them into BRAM, the other one should be implemented in BRAM too. In terms of code there is nothing different in the implementation, only the width/depth.

 

 If synthesis decides either of the instances has tied off inputs, or outputs that are unused - it'll optimize your logic down to about nothing.

All outputs are being used in both.

 

Are you synthesizing a full design, or just some sub-modules?  If the latter, did you specify OOC synthesis?

I'm synthesizing full design in order to know how much LUTs i need to implement it in a FPGA. I will try to synthesize the submodule.

 

-----------------------------

 

Edit: I changed a define that don't affect this instantiations and the first instance (+38.000 cells) converts to +6000. I don't know what is happening, or what Vivado is doing, that's so strange!

 

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Scholar markcurry
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Registered: ‎09-16-2009

Re: [How can it be possible?]

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@joel.sanchezwrote:

 

You mention arrays - could one instance be inferring BRAMs, but the other LUTs? (For whatever reason).

I have enough BRAM and both arrays have pretty the same size so if it put one of them into BRAM, the other one should be implemented in BRAM too. In terms of code there is nothing different in the implementation, only the width/depth.

 


Be aware that synthesis can often make unexpected decisions - sometimes based on just something as simple as width or depth.  You may need to investigate the synthesis log files to be sure.  You likely have an idea in your head of what should may to BRAM and what should may to FFs, and LUTs.  Check the logfiles for some of the top candidates and confirm.

 


@joel.sanchezwrote:

 

Are you synthesizing a full design, or just some sub-modules? If the latter, did you specify OOC synthesis?
 

I'm synthesizing full design in order to know how much LUTs i need to implement it in a FPGA. I will try to synthesize the submodule.

 


I'd stick with what you have and just diagnose with your current top-level synthesis.  (You may change what you're trying to diagnose by changing your flows).

 

What sort of flatten_hierarchy , synthesis options are you using?  If you're using -flatten_hierarchy rebuilt, (or flat), then synthesis will optimize across boundaries.  If your two blocks share a lot in common, or are redundant in some other way, synthesis will optimize quite a bit.  The reports may seem off if it's leaving the "common" logic in one instance (shared with the other).

 

Regards,

 

Mark

Explorer
Explorer
1,581 Views
Registered: ‎01-23-2018

Re: [How can it be possible?]

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Hi @markcurry,

 

I have been checking log files, but I didn't see anything strange, should I look for some specific message or there is a way to see what optimizations Vivado did during the synthesis?

 

I make the synthesis with OOC modules and both instances give similar values on cell usage.

 

Also, I implemented an ifdef that allows to make one part of the design smaller and it does that the instance which uses more than 38.000 cells goes down to 6500 cells, and this define DON'T affect this instance.

 

I really don't know what is happening. I'm using the default values for synthesis I didn't change anything.

 

 

Thanks.

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Explorer
Explorer
1,533 Views
Registered: ‎09-07-2011

Re: [How can it be possible?]

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Is the problem that the "first file" is bigger than expected? Or, that the "second file" is smaller than expected?

 

What are they in isolation?  600/2 vs 550/2

 

 

Explorer
Explorer
1,486 Views
Registered: ‎01-23-2018

Re: [How can it be possible?]

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Hi @geoffbarnes,

 

 both files have similar size, 654KB vs 652KB. Also, I'm looking into the log file and I don't find nothing different on the module instantiation.

 

 

 

Regards,

 

Joel

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Explorer
Explorer
1,468 Views
Registered: ‎09-07-2011

Re: [How can it be possible?]

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Meant the size of the module you are instantiating.     It's unclear if the module should be ~3400 or ~34000 cells or whatever metric.

 

If you take the module and synthesis in isolation, what resource usage do you get?   (Repeat for the parameter settings you're interested in). 

 

 

 

Explorer
Explorer
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Registered: ‎01-23-2018

Re: [How can it be possible?]

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Hi @geoffbarnes,

 

 

1. The multiple instantiation(~3500 cells usage/instance) have next inputs: 540 bits 2 words .

 

2. The second instantiation which is used only once (~35.000 cells usage)  have the next inputs: 580 bits 2 words. 

 

I synthetized both and give similar results, but if I use my top level module it gives the big difference meant before except if I enable a define that does not affect this portion of code, with that define the second instantiation become to ~6000 cells. It's so strange.

 

 

Regards,

 

Joel

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Explorer
Explorer
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Registered: ‎09-07-2011

Re: [How can it be possible?]

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It's good to check the block inputs as well. 

 

The synthesizer can sometimes optimise when the same nets fan out to the inputs of multiple instances of the same block.

Explorer
Explorer
1,016 Views
Registered: ‎01-23-2018

Re: [How can it be possible?]

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Hi @geoffbarnes,

As soon as I have the fpga I will try if it is affects the performance.

 

 

Thanks

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Moderator
Moderator
1,927 Views
Registered: ‎07-21-2014

Re: [How can it be possible?]

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@joel.sanchez

 

One simple check that you can perform is: Apply DONT_TOUCH in the module where "generate" block is used and this will stop any optimizations(if any).

 

Thanks,

Anusheel

Explorer
Explorer
988 Views
Registered: ‎01-23-2018

Re: [How can it be possible?]

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Hi @anusheel,

 

thank you I didn't know it. I will mark it as solved.

 

 

Thank you so much to all of you who helped me. Hope you have a nice day/night!

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