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Observer liwenrui
Observer
7,765 Views
Registered: ‎06-24-2011

How disable file operation when synthesize?

The simulation writes data to files.  Synthesize is started when isim is running.  The synthesize looks like "excute" the file related code in the vhdl, which is not supposed to.  The problem is the simulation file result is ruined by synthesize process.

 

My question is:

 

How do I disable the "excution" of file code when synthesize?

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7 Replies
Historian
Historian
7,749 Views
Registered: ‎02-25-2008

Re: How disable file operation when synthesize?


@liwenrui wrote:

The simulation writes data to files.  Synthesize is started when isim is running.  The synthesize looks like "excute" the file related code in the vhdl, which is not supposed to.  The problem is the simulation file result is ruined by synthesize process.

 

My question is:

 

How do I disable the "excution" of file code when synthesize?


You don't.

 

You write synthesizable source code, and when you simulate and verify it, the test bench handles the file operations.

----------------------------Yes, I do this for a living.
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Observer liwenrui
Observer
7,643 Views
Registered: ‎06-24-2011

Re: How disable file operation when synthesize?

thanks for reply.  

 

All I am doing for this is to change the file path in the code when I synthisize the system to prevent the synthisizer from ruinning the file result that the isim is writing in.  The result is good but the way is stupid. 

 

Now I have a new problem.  I have a dynamic file name with file_open in the simulation:

 

         text_file_name(text_file_name'right-5) :=  character'val(conv_integer(frame_cnt_10+48));

         file_open(v_wr_file, text_file_name, write_mode);

 

which is fine for the isim running and get what I need.  But when I run synthisis, the system gives an error that it cannot have the dynamic file name and stops.  Again, I commented this file_open line and the synthisizer works again. 

 

My quesion is:  how the system can disable really to check the file operation code in the synthisizer? it is strongly not supposed to be done in the synthizer. 

 

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Historian
Historian
7,639 Views
Registered: ‎02-25-2008

Re: How disable file operation when synthesize?


@liwenrui wrote:

thanks for reply.  

 

All I am doing for this is to change the file path in the code when I synthisize the system to prevent the synthisizer from ruinning the file result that the isim is writing in.  The result is good but the way is stupid. 


ISE's project manager lets you select whether a source file is used for synthesis, for simulation, or for both.


Now I have a new problem.  I have a dynamic file name with file_open in the simulation:

 

text_file_name(text_file_name'right-5) := character'val(conv_integer(frame_cnt_10+48));

file_open(v_wr_file, text_file_name, write_mode);

 

which is fine for the isim running and get what I need.  But when I run synthisis, the system gives an error that it cannot have the dynamic file name and stops.  Again, I commented this file_open line and the synthisizer works again. 

My quesion is:  how the system can disable really to check the file operation code in the synthisizer? it is strongly not supposed to be done in the synthizer. 


If the source file is meant for synthesis, you cannot put those file-handling functions in the source. PERIOD. If the source file is truly meant for simulation only, tell the ISE project manager that.

----------------------------Yes, I do this for a living.
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Observer liwenrui
Observer
7,627 Views
Registered: ‎06-24-2011

Re: How disable file operation when synthesize?

Thanks a lot, bassman.

 

Yes, the file-handling code is only for simulation but they are necessory to be in the vhdl files that for synthesis  and is not able to be put in the top test bench file. 

 

So, what can I do to "tell" the ISE manage that?

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Mentor hgleamon1
Mentor
7,620 Views
Registered: ‎11-14-2011

Re: How disable file operation when synthesize?

You can change the source file association to "simulation" rather than "implementation" or "all".

 

In the Design Hieracrhy window of Project Navigator, right click the source file in question, choose Source Properties and then choose the drop down list for File Association.

 

I agree with Bassman, though. Just don't put these kind of constructs in components below the test bench.

 

Regards,

 

Howard

 

 -- edit

 

If you REALLY need to have the (approximately) same file for synthesis and simulation, you'll need to find some way to stop the synthesiser from analysing the file reading lines. You could use a module level GENERIC that indicates that you are running a simulation or not and then use a GENERATE statement based on the value of the GENERIC to instantiate the relevant code.

 

It may be possible to use some sort of pragma control but I don't know much about that ...

 

 -- end edit

----------
"That which we must learn to do, we learn by doing." - Aristotle
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Visitor tillnorbert
Visitor
7,609 Views
Registered: ‎09-16-2011

Re: How disable file operation when synthesize?

Hi liwenrui,

 

If you would like to hide a piece of code from xst you can use the translate_off and translate_off constraints. It works like this: 

 

VHDL

-- synthesis translate_off

...code not synthesized...

-- synthesis translate_on

 

Verilog

// synthesis translate_off

...code not synthesized...

// synthesis translate_on

 

(see page 308 [1]).

 

[1]:XST User Guide for Virtex-4, Virtex-5, Spartan-3, and Newer CPLD Devices; UG627 (v 14.5) March 20, 2013

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Observer liwenrui
Observer
7,602 Views
Registered: ‎06-24-2011

Re: How disable file operation when synthesize?

Thanks guys.

 

Yes, It is feasible to use a generic parameter to stop the synthesizer processing the file related code.  

But the thing is that I have tons of place to change and they in very deep level of the code.  to do this , i have to add generic for all the files and all the file related code part.

 

For the changing Source Properties to simulation only, it does not work because the synthesizer cannot the file either when synthesis and then it stops since the file is "in" the code tree instead of out of the top level.

 

Thanks tillnorbert,  the line -- synthesis translate_off/on make the synthesizer work with the dynamic file name.  But in that case the synthesizer still cleans up the file that the simulator is writting in.  

 

Here is what I did:

0. wrape one of the file related code within -- synthesis translate_off/on pair.

1. run the isim to simuate the system for some time, like 100 us, 

2. pause isim,

3. check the simulated result file, and the file is pretty.

4. run the synthesizer successfully and this time the GNC is generated sucessfully.

5. check the same simulated result file,  and it is cleared, nothing in that file !!!!

 

 

 

 

 

 

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