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wsipak
Contributor
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Registered: ‎03-05-2019

How do I create code-based design without block design for Zynq?

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Hello,

I am working with Vivado and I can successfully create a black design, add/connect IPs and generate bitstream.

I'd like to have a code-based (Verilog) design, instead of the block design. As a simple example, let's say I want to create a design with just the instance of ZYNQ7 Processing System (without bd). How do I do this? Is this possible to instantiate the PS in Verilog? Also, the source code of PS isn't public, right?

I haven't found any example project without block design. If such thing exists, please redirect me to it.

A simple example with just the one IP should be enough for me to apply it for a bigger project, thanks a lot!

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anusheel
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Registered: ‎07-21-2014

@wsipak 

You can use the IP Catalog directly(outside of IPI/Block Design) --> search for PS in the IP Catalog --> Double click and then customize the PS as per your requirements --> Generate output products --> Now use the generated Verilog file which consists of the PS instantiation --> copy-paste the instantiation in your design and provide the necessary connections 

Thanks
Anusheel 

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florentw
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Moderator
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Registered: ‎11-09-2015

HI @wsipak 

First keep in mind that when you had the ZynqPS in vivado there is no source code. The ZynqPS is already a part of the silicon. When you add it in vivado it is more it's representation that you add.

One way you can work around the fact that you do not want ot use BD is to use the BD only to instantiate the Zynq. Then you use it as if it was an IP. You can instantiate the BD inside your RTL code


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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anusheel
Moderator
Moderator
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Registered: ‎07-21-2014

@wsipak 

You can use the IP Catalog directly(outside of IPI/Block Design) --> search for PS in the IP Catalog --> Double click and then customize the PS as per your requirements --> Generate output products --> Now use the generated Verilog file which consists of the PS instantiation --> copy-paste the instantiation in your design and provide the necessary connections 

Thanks
Anusheel 

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bitjockey
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Registered: ‎03-21-2011

Is there any way to get a vhdl component also/instead of the verilog?  I found the verilog but maintaining a vhdl one by hand is tedious.

Also, the software suite seems to really want you to make your hdl code be an "IP" module inside the top BD.  you can do the reverse: make the PS block be IP inside your hdl top-level.  But it seems like you have to fight the tool's natural proclivities some. 

Perhaps due to corporate management level beliefs that actual hdl authors are few and far between and they think we'll soon all be dragging and dropping boxes and running connection wizards all day.

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