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rex_nyu
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How do I know if my adder had been packed into DSP48E slices

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Hi all,

 

I have an FIR design (4 taps). It contains 4 multipliers and 3 adders. After synthesis for Vetex-5 LX110T using xst, I can see 4 DSP48E slices are used and it is obvious that the multipliers are packed into the DSP48E slices. But how do I determine if the three adders are also packed in to the slices? Is there any generic method to know what is being used in a DSP slices (especially when the design is large) .

 

Thank you very much!

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rex_nyu
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I found an easy way to figure it out. Use FPGA editor, just observe the DSP48E connections. But thank both of you for the concrete answers.

View solution in original post

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evgenis1
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Hi,

 

One method is checking MAP report - "Area group" and "Utilization by hierarchy" sections. See attached sample screenshots.

 

Thanks,

Evgeni

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map1.jpg
evgenis1
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Another screenshot

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map2.jpg
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rex_nyu
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Thank you for your quick answer! The picture you attached makes sense. However, what is the ISE version you are using? I am using ISE 12.2 and I check my map report. First, It is a plaintext report (not as vivid as yours, but that is ok). Second, I found no information in the area group and partition summary session (see below)

 

Section 9 - Area Group and Partition Summary--------------------------------------------


Partition Implementation Status-------------------------------
  No Partitions were found in this design.
-------------------------------

 

Area Group Information----------------------
  No area groups were found in this design.
----------------------

 

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evgenis1
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Hi, 

 

I'm using my own web-based tool called ReportXplorer to view this. Area groups show only those floorplanned regions that fall under AREA_GROUP constraint,and partitions. You might not have those in your design.

In order to view "Utilization by hierarchy", you need to enable -detail MAP option.

 

Thanks,

Evgeni

 

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rex_nyu
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I enable the option and now I can see the same view as yours. 

 

But I still have one concern. 

 

It shows me something like below:

 

DSP48E

  4/4 

 

This number seems to mean I use a total of 4 DSP48E slices(the second 4) and this module use 4 DSP48E slices (the first 4) out of the total. It does not really tell me whether the adder is packed inside the slices. Could you give me some hints? 

 

 

Thank you!

 

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evgenis1
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More detailed information on how things are synthesized can be found in the synthesis report. 

XST synthesis produces something like in the following example (.syr):

 

=========================================

HDL Synthesis

=========================================

Synthesizing Unit <mult>.Found 16-bit register for signal <c>.

Found 8x8-bit multiplier for signal <a[7]_b[7]_OUT>

Summary:inferred 1 Multiplier(s).inferred 16 D-type flip-flop(s).

Unit <mult> synthesized.

============================================================

Advanced HDL

============================================================

Synthesizing (advanced) Unit <mult>.

Found pipelined multiplier on signal <a[7]_b[7]_OUT>:1

pipeline level(s) found in a register connected to themultiplier macro output.

Pushing register(s) into the multiplier macro

===========================================================

Advanced HDL Synthesis ReportMacro Statistics

# Multipliers : 18x8-bit registered multiplier : 1

===========================================================

 

Synplify produces a similar report to this.

 

 

Thanks,

Evgeni

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rex_nyu
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This helps. My design is not big (4 tap FIR) and the Advanced HDL synthesis info is here. Can I safely assume that the adders are not being pushed to the DSP48E slices? 

 

 

=========================================================================

*                       Advanced HDL Synthesis                          *
=========================================================================
Synthesizing (advanced) Unit <fir_filter_golden_proc>.
Found pipelined multiplier on signal <conv_u2u_16_16_2_conv_u2u_16_16>:
- 2 pipeline level(s) found in a register on signal <fir_filter_golden_regs_regs_E2_sva_read_dft>.
Pushing register(s) into the multiplier macro.
Found pipelined multiplier on signal <conv_u2u_16_16_1_conv_u2u_16_16>:
- 2 pipeline level(s) found in a register on signal <fir_filter_golden_regs_regs_E1_sva_read_dft>.
Pushing register(s) into the multiplier macro.
Found pipelined multiplier on signal <conv_u2u_16_16_4_conv_u2u_16_16>:
- 1 pipeline level(s) found in a register on signal <fir_filter_golden_regs_regs_E0_sva>.
Pushing register(s) into the multiplier macro.
INFO:Xst:2385 - HDL ADVISOR - You can improve the performance of the multiplier Mmult_mul_n16_l16_1_itm_mult0001 by adding 2 register level(s).
INFO:Xst:2385 - HDL ADVISOR - You can improve the performance of the multiplier Mmult_mul_n16_l16_itm_mult0001 by adding 2 register level(s).
INFO:Xst:2385 - HDL ADVISOR - You can improve the performance of the multiplier Mmult_mul_n16_l16_3_itm_mult0001 by adding 2 register level(s).
Unit <fir_filter_golden_proc> synthesized (advanced).
=========================================================================

 

Advanced HDL Synthesis Report
Macro Statistics
# Multipliers                                          : 4
 9x9-bit multiplier                                    : 1
 9x9-bit registered multiplier                         : 3
# Adders/Subtractors                                   : 3
 17-bit adder                                          : 2
 18-bit adder                                          : 1
# Registers                                            : 58
 Flip-Flops                                            : 58
=========================================================================

 

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : fir_filter_golden.ngr
Top Level Output File Name         : fir_filter_golden
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : No
Design Statistics
# IOs                              : 62
Cell Usage :
# BELS                             : 147
#      GND                         : 1
#      LUT2                        : 17
#      LUT3                        : 47
#      LUT4                        : 1
#      LUT6                        : 14
#      MUXCY                       : 33
#      VCC                         : 1
#      XORCY                       : 33
# FlipFlops/Latches                : 58
#      FDR                         : 26
#      FDRE                        : 32
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 61
#      IBUF                        : 42
#      OBUF                        : 19
# DSPs                             : 4
#      DSP48E                      : 4
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evgenis1
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Another option to control whether the logic is pushed into DSP48 or not is by using use_dsp48 XST synthesis constraint. 

 

It has to be placed before the instance, module or signal declaration (in Verilog code):

  (* use_dsp48 = "{auto|automax|yes|no}" *)

 

For more information, look it up in the XST User Guide.

 

Using use_dsp48 = no option will prevent XST from pushing your adders into DSP48.

 

 

Thanks,

Evgeni

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ywu
Xilinx Employee
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Registered: ‎11-28-2007

You can use ADEPT to extract all DSP48 instances and their attributes from a NCD (see the snapshot below). You can easily see whether or not an adder is absorbed into an DSP48. Please check the blogs below for more details:

 

Virtex6 DSP48 View

 

Virtex5 DSP48 View

 

ScreenHunter_43.jpg

 


@rex_nyu wrote:

Hi all,

 

I have an FIR design (4 taps). It contains 4 multipliers and 3 adders. After synthesis for Vetex-5 LX110T using xst, I can see 4 DSP48E slices are used and it is obvious that the multipliers are packed into the DSP48E slices. But how do I determine if the three adders are also packed in to the slices? Is there any generic method to know what is being used in a DSP slices (especially when the design is large) .

 

Thank you very much!




Cheers,
Jim
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rex_nyu
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Registered: ‎08-12-2011

I found an easy way to figure it out. Use FPGA editor, just observe the DSP48E connections. But thank both of you for the concrete answers.

View solution in original post

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