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Visitor
Visitor
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Registered: ‎03-18-2020

How to Get Original Signals of A Synthesized LUT

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Hi all,

 

    I am now trying to resolve some critical path problem and I locate a problem at a LUT6. However, it seems that multiple signals are merged into the LUT and the output signal name is overwritten by one of the involved signal. This situation is common for some FSM control signals.

    Therefore, I wonder whether there is a Tcl command that can help me to find the original signals in the design for a specific LUT?

    THANKS IN ADVANCE!!!

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-14-2008

The "Go to Source" function is only supported in GUI.

-vivian

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Scholar
Scholar
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Registered: ‎08-01-2012

Vivado has a habit of using some strange names when it does logic reduction.

Unfortunately, there is no way to recover the names. The only way is to keep your names is to use the DONT_TOUCH or MARK_DEBUG attributes on a signal, and it will not be merged during logic reduction. This will change the circuit produced.

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Visitor
Visitor
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Registered: ‎03-18-2020

Hi @richardhead ,

 

Thanks a lot for your prompt reply! Then I try to walk around.

I notice that the Vivado 2019.2.1 GUI allows us to trace back to the source code by clicking "Go to Source (F7)". I wonder whether there is a Tcl command for such functionality to print out something like "the cell can be traced back to xxxx".

I guess this is not a common demand but I just find a possible solution.

 

THANKS AGAIN! ^_^

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Xilinx Employee
Xilinx Employee
337 Views
Registered: ‎05-14-2008

The "Go to Source" function is only supported in GUI.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------

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