I have a LIB file to add and use in my verilog design. It has PVT Characterization, relating input, and output characteristics, timing, power, noise.
How can I do this ?
Thanks in advance.
Hi @ehsan.aerabi, Vivado supports XDC files, which have some Synopsys SDC based timing constraints. You can refer to UG903 (attached below) to see what commands can be used: