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Visitor
Visitor
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Registered: ‎04-12-2019

How to add Liberty Timing File (LIB) to Vivado and use it in my synthesis

I have a LIB file to add and use in my verilog design. It has PVT Characterization, relating input, and output characteristics, timing, power, noise. 

How can I do this ? 

 

Thanks in advance. 

Ehsan

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Xilinx Employee
Xilinx Employee
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Registered: ‎02-13-2020

Re: How to add Liberty Timing File (LIB) to Vivado and use it in my synthesis

Hi @ehsan.aerabi

Vivado supports XDC files, which have some Synopsys SDC based timing constraints. You can refer to UG903 (attached below) to see what commands can be used: 

 https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug903-vivado-using-constraints.pdf

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