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Visitor
894 Views
Registered: ‎06-07-2012

## How to change a signal on two phases of the clock

I'm new to verilog and FPGAs.

I have a signal I need to change on different phases of a clock.

This is just an example to ask my question

reg Sig1;

Clock B is delayed from Clock by X number of degrees (amount does not matter here)

always @ (posedge Clock_A)

Sig1 <= 1'd0;

always @ (posedge Clock_B)

Sig1 <= 1'd1;

Assign Signal_Out = Sig1;

ISE (Spartan 6 design) produces an error - "connected to following multiple drivers:"

Can someone explain how I might accomplish this.

Thanks

1 Solution

Accepted Solutions
Visitor
605 Views
Registered: ‎06-07-2012

## Re: How to change a signal on two phases of the clock

Thanks for the help.

I revised my design so as I to require 3 clocks (same frequency - just phase shifted).

I have moved to a single clock - faster than my previous attempt at 3 clocks - and now count clock edges to get to the delay I require.

This question can be closed.

9 Replies
Voyager
859 Views
Registered: ‎02-01-2013

## Re: How to change a signal on two phases of the clock

You're supposed to assign a value to a reg in only one always block.  You're doing it in two.

It looks like you want to use an ODDR2:

-----------------------------------------------------------------

ODDR2 #(
.DDR_ALIGNMENT("NONE"),
.INIT(1'b0),
.SRTYPE("SYNC")
) ODDR2_inst (
.Q( Signal_Out ),
.C0( Clock_A ),
.C1( Clock_B ),
.CE( 1'b1 ),
.D0( 1'b0 ),
.D1( 1'b1 ),
.R( 1'b0 ),
.S( 1'b0 )
);

-----------------------------------------------------------------

Check it out in the Spartan-6 FPGA SelectIO Resources User Guide (UG381).

-Joe G.

Visitor
855 Views
Registered: ‎06-07-2012

## Re: How to change a signal on two phases of the clock

Thanks for the reply.

I know what the issue is.

An ODDR2 is not what I need.

I'm hoping someone knows a way to work around this simple example and enable timing from two clocks to generate a signal.

Thanks.

Voyager
789 Views
Registered: ‎02-01-2013

## Re: How to change a signal on two phases of the clock

I'm glad you know what the issue is. I get sad when people don't share it.

If you just want correct Verilog to do what your original code looks like it was trying to do, it's:

----------------------------------------------------------------------

always @ (posedge Clock_A or posedge Clock_B)

if ( Clock_A )

Sig1 <= 1'd0;

else

Sig1 <= 1'd1;

----------------------------------------------------------------------

This isn't what you originally asked for, but it's the only way to get the 'logic' you seem to want. Effectively, Clock_A will become an asynchronous reset and Clock_B will be the true clock. If you try to actualize this, operational behavior will vary if the phase between Clock_A and Clock_B gets too small.

-Joe G.

P.S. If you're trying to build a digital phase detector, this is the wrong approach.

Visitor
768 Views
Registered: ‎06-07-2012

## Re: How to change a signal on two phases of the clock

Thanks Joe - I was not trying to be a smart ass.

I kept the question simple - my actual requirement required 3 clocks.  I knew there was not an existing model to handle my situation - I was hoping for some fancy code work-around.

I resolved to using a faster clock and then counting edges in to determine delay position and make the signal change - that way all changes occur in one always statement and are associated with a single clock.

My trying to simplfy my question actually turned out to be a hindrance.

I was actuall trying to mimic a strategy I use in a cpu to create a WS2811 (pixel) bit stream.  In a cpu you can have 3 pwm signals of different phases and then change the output signal based on the clock edge of a specific clock.  I tried to implement that methodology into my fpga solution - which was what lead to this question.

Not everything you can do in cpu software is directly capable of being implemented in fpga hardware - one lesson learned!

Thanks for trying.

Joe

Scholar
668 Views
Registered: ‎08-01-2012

## Re: How to change a signal on two phases of the clock

FPGA fabric only allows single clocked registers.

Are you sure you want multiple clocks? The usual way to do this would be with multiple clock enables.

Scholar
651 Views
Registered: ‎04-26-2015

## Re: How to change a signal on two phases of the clock

@jhinkle If you do it in a microcontroller, all those timers are running from the same clock - just with different prescalers. You can easily achieve that with an FPGA, and it'll be a much better solution to the problem than running three separate clocks.

Scholar
617 Views
Registered: ‎07-09-2009

## Re: How to change a signal on two phases of the clock

Basicaly, in an FPGA its not possible to use both edges of a clock on a flip flop.

The physical silicon does not support this, ( apart from the IO blocks as already discussed )

There are many ways of supporting multiple clocks and designing systems that can simulate multiple clocks, they are all a fudge, typicaly involving multiple paths, and being very specific to a design

A PLL Phase Detector as mentioned is a typical example of "it would be great if we had mutliple edge clocks", but there are ways around .

Can we have some more details on the application, and we might be able to help,

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Visitor
606 Views
Registered: ‎06-07-2012

## Re: How to change a signal on two phases of the clock

Thanks for the help.

I revised my design so as I to require 3 clocks (same frequency - just phase shifted).

I have moved to a single clock - faster than my previous attempt at 3 clocks - and now count clock edges to get to the delay I require.

This question can be closed.

Moderator
524 Views
Registered: ‎03-16-2017