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gsemeraro
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Registered: ‎04-02-2020

How to configure IP Integrator for GLOBAL synthesis from tcl script

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I have a non-project based development (i.e., entirely built from tcl scripts, Vivado GUI is not used) and I need to configure some IP blocks (created in Simulink using HDL Coder and System Generator) to be synthesized with the top-level so that I can set constants that will propagate into the IP resulting in unused logic being trimmed away.  All the IP blocks are generated with out-of-context synthesis and I can't get any/all of them to use global synthsis.  I have tried to set GENERATE_SYNTH_CHECKPOINT to false but that requires IS_MANAGED  to be false first and that cannot be done because the parent isn't un-managed.  The parent is the top-level which doesn't accept the IS_MANAGED flag (that can only be set on xci and dcp files but the top-level doesn't have one of those).

Is there a way, using tcl command(s) to configure the synthesis for the entire design to use GLOBAL and not out-of-context (OOC) mode?  I can see that there is a selection in the GUI (under "IP Integrator...Generate Block Design) but I need to do it from a tcl script.

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miker
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Registered: ‎11-30-2007

@gsemeraro 

Have you referenced the Vivado Design Suite Designing IP Subsystems Using IP Integrator User Guide (UG994; v2020.2) in Chapter 4: Working with Block Designs in section Using the Generate Output Products Dialog Box?  It highlights the equivalent tcl command.

forums_synth_checkpoint_mode.png

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miker
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Registered: ‎11-30-2007

@gsemeraro 

Have you referenced the Vivado Design Suite Designing IP Subsystems Using IP Integrator User Guide (UG994; v2020.2) in Chapter 4: Working with Block Designs in section Using the Generate Output Products Dialog Box?  It highlights the equivalent tcl command.

forums_synth_checkpoint_mode.png

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gsemeraro
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Thanks!  I didn't see that tcl command.  I will give that a try.  Thanks.

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gsemeraro
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Ok, so that worked in the sense that I think it is synthesizing globally but it through another error that I don't know what to do with...all of the custom IP blocks, except for this failing one, is created as a Simulink model and generated with either HDL Coder or System Generator.  This failing one is an IP block but it was hand written in VHDL.  Not sure why this one isn't being handled properly because it is when synth_checkpoint_mode is not set to anything (which would be it is using Hierarchy which is OOC).

 

ERROR: [DRC INBB-3] Black Box Instances: Cell '<<RedactedName1>>_i/<<RedactedName2>>_0/U0' of type '<<RedactedName2>>' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.

 

I found this thread:

https://forums.xilinx.com/t5/Design-Entry/quot-DRC-INBB-3-Black-Box-Instances-quot-Unable-to-instantiate/m-p/803727#M14825

Which makes sense but I don't know where to find the IP names that might be mis-matched...and I'm not sure that is the problem because everything is fine if I use OOC.

 

Any insight / assistance would be greatly appreciated...

 

Thanks,

Greg

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gsemeraro
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Additional info...I'm seeing a rather haphazard use of category and taxonomy in the hand-written IP blocks (of which this design has a handful).  Does that matter at all?  Is the category and/or taxonomy used for anything other than browsing the IP within the GUI?

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miker
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Registered: ‎11-30-2007

@gsemeraro 

Is the VHDL file that is causing the issue added to the Block Design using "Add Module" rather than Packaging the IP?

Are you still adding that to your block design using create_bd_cell -type module -reference <vhdl_entity_name> <reference_name>?

For example, I created a dff.vhd module that Vivado added using:

create_bd_cell -type module -reference dff dff_0?

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miker
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@gsemeraro 

I don't think the category and taxonomy will cause any function problems... just poor library management (...like you said, for browsing the IP within the GUI).

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gsemeraro
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The VHDL is added (in the top-level tcl script exported from the GUI) as IP:

  set Exxxxx_0 [ create_bd_cell -type ip -vlnv company.com:companyIpCores:Exxxxx:1.0 Exxxxx_0 ]

 

On a lark, I left the tcl loop to synthesize all the IP OOC in place (previously I had commented that out) but THEN did the global synthesis after that loop.  This gave a different error
ERROR: [IP_Flow 19-993] Could not find IP file for IP '<<RedactedName>>'.

warning above this error suggested to re-generating the IP, attempting to do that. 

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gsemeraro
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Regenerating (via package.tcl script) didn't change anything.  My fundamental problem seems to be that the IP block is considered a black box and global synthesis cannot deal with that (which makes perfect sense) so I need to understand how to resolve the IP being black box...any assistance would be greatly appreciated.

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gsemeraro
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@miker I looked through all the forum topics for "Black Box" - none are applicable: there are no syntax errors in the module (none shown in GUI and the block builds fine in OOC mode), the IP isn't out-of-date (reported as up-to-date in "Report IP Status", the name is not mis-matched (again, works fine in OOC mode) and I can't change to OOC mode to eliminate the error as one of the posts suggest because I'm specifically trying to use global synthesis.

 

I also built this FPGA in the GUI and get the same black box error in the implementation phase as I get with my tcl scripts.  The error message from the GUI is the same with no additional information.

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