UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer songdeway
Observer
549 Views
Registered: ‎06-25-2019

How to connect debug signal wires based on a synthesized design while no need re-synthesize the design?

Jump to solution

Hi,

Design tool : Vivado 2018.2

Sometimes for a synthesized design, we have to connect internal signal wires or regs to the debug core or ILA core. So how could we do this based on a synthesized design while do not need re-synthesized the design with debug core or ILA?

If someone know the answer, please give me a response.

Thanks !

 

0 Kudos
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
402 Views
Registered: ‎05-14-2008

Re: How to connect debug signal wires based on a synthesized design while no need re-synthesize the design?

Jump to solution

The net name is "rst_IBUF", not "debug_test/rst_IBUF" if debug_test is your top level.

You can refer to the correct net name in the net properties window.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
16 Replies
Xilinx Employee
Xilinx Employee
545 Views
Registered: ‎05-14-2008

Re: How to connect debug signal wires based on a synthesized design while no need re-synthesize the design?

Jump to solution

Are you using the flow of instantiating ILA core in your RTL for debugging?

Another way to use ILA core is using the "Set up Debug" wizard in the Synthesized design.

You can choose/change the nets to be connected to the ILA core.

And at this stage you don't need to re-synthesize the design. The tool will insert the ILA logics automatically.

For more details, please refer to UG908.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
0 Kudos
Observer songdeway
Observer
523 Views
Registered: ‎06-25-2019

Re: How to connect debug signal wires based on a synthesized design while no need re-synthesize the design?

Jump to solution

Hi Vivian,

I'm glad you replied me so quickly.

I don't instantiate ILA core or add 'MARK_DEBUG' in my code because sometimes I am not sure which signals are in trouble. For 'Set Up Debug', when finish this step, if I ignore 'reload' operation, the implementation flow gonna be failed due to missing debug wires. But if I reload the design, the tool will re-synthesize the design.

How to do this : 'You can choose/change the nets to be connected to the ILA core.'

Could I find the answer in reference UG908?

Many thanks !

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
504 Views
Registered: ‎05-14-2008

Re: How to connect debug signal wires based on a synthesized design while no need re-synthesize the design?

Jump to solution

Reload does not re-synthesize the design but just refresh the opened synthesized design.

A tip here is to create a seperate XDC file, add this xdc to the project, set it as the target xdc and set its used_in property to "Implementation".

In this way, when you finish "set up debug" and save constraints to the target xdc, the Synthesis run will not become out-of-date.

You can specify (by searching and selecting) nets in the Set Up Debug wizard for debug and can also remove previous selected nets.

You can find the info in UG908.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
Tags (2)
Observer songdeway
Observer
488 Views
Registered: ‎06-25-2019

Re: How to connect debug signal wires based on a synthesized design while no need re-synthesize the design?

Jump to solution

By the way,

I heard from my colleague that for Xilinx ISE, a function called 'fpga_edit' allows you to edit debug probes after implemetation step, you don't have to re-routing the design.

Does Vivado has function like this ?

0 Kudos
Xilinx Employee
Xilinx Employee
477 Views
Registered: ‎05-14-2008

Re: How to connect debug signal wires based on a synthesized design while no need re-synthesize the design?

Jump to solution

You can do this in Vivado by using ECO, which is to use tcl commands to modify the connections and routings (maybe placement as well) in the Implemented design.

This is not so straight forward as in Set Up Debug.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
0 Kudos
Observer songdeway
Observer
458 Views
Registered: ‎06-25-2019

Re: How to connect debug signal wires based on a synthesized design while no need re-synthesize the design?

Jump to solution

Hi Vivian,

As you told me, I found a tutorial which tells me how to use ECO in vivado.

However, as I operate as example shown , an error occurs. If I add '-quiet', no error occurs but generated bitstream does not have re-added probe.

You can find more info from attachments. And would you please give me suggestion about correct operation steps ?

 

eco.jpg
example.jpg
0 Kudos
Moderator
Moderator
448 Views
Registered: ‎11-04-2010

Re: How to connect debug signal wires based on a synthesized design while no need re-synthesize the design?

Jump to solution

Hi, @songdeway ,

What the command dose in your snapshot is to connect the internal signal to the FPGA port, instead connecting the signal to the ILA. 

-quiet option is just used to avoid information printing and it will not affect the result of the command.

For the candicate of the -net option, it should be found with "get_nets" in the design and the net should be in FPGA fabric(not in IOB).

 

 

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Xilinx Employee
Xilinx Employee
438 Views
Registered: ‎05-14-2008

Re: How to connect debug signal wires based on a synthesized design while no need re-synthesize the design?

Jump to solution

@songdeway 

The error says the net name "debug_test/rst_IBUF" does not exist in the Implemented design.

How do you get this net name?

You can check the net name by opening the schematic of the logics around the net.

When you select the net in the schematic, its name will be shown in the netlist window and the net properties window.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
0 Kudos
Observer songdeway
Observer
434 Views
Registered: ‎06-25-2019

Re: How to connect debug signal wires based on a synthesized design while no need re-synthesize the design?

Jump to solution

Of course I did open schematic and then got the net name. like attachment shown.

So if I need connect this net (rst_IBUF) to device port AF33, which specified tcl command should I use here? Would you please write the example command here?

The IOSTANDARD is LVCMOS18.

BRs.

schematic.jpg
0 Kudos
Observer songdeway
Observer
428 Views
Registered: ‎06-25-2019

Re: How to connect debug signal wires based on a synthesized design while no need re-synthesize the design?

Jump to solution

Hi @hongh,

Yes I am trying to connect this internal net signal to device port, not ILA.

The attachment shows the whole schematic and hierarchy of this simple design.

So if I need connect this net (rst_IBUF) to device port AF33, which specified tcl command should I use here? Would you please write the example command here?

The IOSTANDARD is LVCMOS18.

BRs.

schematic.jpg
0 Kudos
Xilinx Employee
Xilinx Employee
403 Views
Registered: ‎05-14-2008

Re: How to connect debug signal wires based on a synthesized design while no need re-synthesize the design?

Jump to solution

The net name is "rst_IBUF", not "debug_test/rst_IBUF" if debug_test is your top level.

You can refer to the correct net name in the net properties window.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
Observer songdeway
Observer
392 Views
Registered: ‎06-25-2019

Re: How to connect debug signal wires based on a synthesized design while no need re-synthesize the design?

Jump to solution

Hi Vivian,

Thanks a lot, problem resolved.

BRs.

0 Kudos
Observer songdeway
Observer
347 Views
Registered: ‎06-25-2019

Re: How to connect debug signal wires based on a synthesized design while no need re-synthesize the design?

Jump to solution

Hi @viviany ,

Sorry to disturb you again. Add a probe without re-route to the device port is OK to me, I wonder if I could add the internal signals to the existed ILA core and check the wave in Vivado. Could Vivado do this? If yes, how could I make it?

Thanks.

BRs.

0 Kudos
Xilinx Employee
Xilinx Employee
289 Views
Registered: ‎05-14-2008

Re: How to connect debug signal wires based on a synthesized design while no need re-synthesize the design?

Jump to solution

We don't have existing tcl script or utility like add_probe to do this.

You need to manually use ECO in the implemented design to make the necessary changes.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
0 Kudos
Xilinx Employee
Xilinx Employee
257 Views
Registered: ‎05-14-2008

Re: How to connect debug signal wires based on a synthesized design while no need re-synthesize the design?

Jump to solution

@songdeway 

One more information for you.

You can use "modify_debug_ports" to change the ILA probes post implementation.

For details, please refer to UG908.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
0 Kudos
Observer songdeway
Observer
249 Views
Registered: ‎06-25-2019

Re: How to connect debug signal wires based on a synthesized design while no need re-synthesize the design?

Jump to solution

@viviany

 

Yeah I found specified tcl commands according to UG835, for adding, deleting or modifying internal signals to ILA probe ports.

Of course appreciate your reference UG908.

BRs.