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Visitor
Visitor
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Registered: ‎03-18-2020

How to display the contents of an FSM

Hello,

Is there a way to show the contents of an FSM?. Please find attached the FSM block. I know that my FSM consists of a 3-bit register from the synthesis report but what I don't know is how the signals _n0083(0), _n0083(1) and _n0087 are configured in RTL.

By the way, I am using ISE 14.7. 

 

Any help would be greatly appreciated.

FSM block.PNG
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Xilinx Employee
Xilinx Employee
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Registered: ‎02-12-2020

Hi @Sultan1 ,

Can you try the below FSM settings to avoid FSM encoding and share the FSM block after applying the setting?

fsm.png

Thanks,
-RomisaaS

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Teacher
Teacher
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Registered: ‎07-09-2009

The very best way is to simulate the RTL, and then you will see the state names.

As a background, FPGAs have various ways of "encoding" states.

The "best" normaly, is to let the tools work out the best encoding, as the different methods have pros and cons for speed, area et all.

e.g.
http://www.csun.edu/edaasic/roosta/SME_Tech.pdf
https://core.ac.uk/download/pdf/61743673.pdf


You have the option in say VHDL to pre define the states yourself as binary numbers, or let the tools make their own.

https://www.xilinx.com/support/documentation/sw_manuals/help/iseguide/mergedProjects/destech/html/cd_fsm.html

look at the encoding line

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254 Views
Registered: ‎06-21-2017

When I build a complicated state machine, I often add in an enumerated code I understand.  I put in a unique value in every state and take this to an output port of the FSM module.  This can be seen in the simulator and it can go to an ILA.  When I take the ILA out, I just leave the port OPEN.  The synthesis tool will remove the extra logic in the final product.

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