How to find the board name parameter in Verilog before synthesis?

[rty_t8]

Hello.

I need to make conditional Verilog code depending on board name parameter (Project Settings/Projects device/Boards).

Something like:

generate

if ($get_board == "U200")

module1();

else

module2();

endgenerate

I know how to find the board name in TCL (current_board_part).

But I don't know how to find this parameter in Verilog/System Verilog.

I can't run TCL script before synthesis to make include file.

Is it possible to run TCL command from Verilog and receive return value back in Verilog?

Are there some Verilog constant for current used board?

Thank you in advance for answers.

[apetley]

Hi @rty_t8 ,

There is no way to refer to TCL constant/variable from verilog or for that matter in synthesis.

I guess you have two different designs/configurations targeted to two different boards say U200 and U250

At any given time only one module will be used , subsequently syntheszied implemented and downloaded to board. 

You can use of `define of which value you can pass along with synth_design switch

`ifdef U200

`define get_board U200

`elsif U250

`define get_board U250

`endif

generate

if (`get_board == "U200")

module1 U1();

else

module2 U1();

endgenerate

synth_design -verilog_define U200=yes

Alternately, you can also pass board name as TCL argument using -tclargs

Please refer https://www.xilinx.com/support/answers/56501.html

Thanks,

Ajay