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Registered: ‎10-21-2008

How to make XST synthesis an ADDER to a fast architesture?

Hi:

  I have a problem with the XST synthesis tool.

  There is a critical paht in my design. This path include a 13 bits adder. From the timing report, it seems that XST use carry-ripple architecture to implemnet this function. How to force XST to use a high speed ADDER architecture to implement this function, such as carry-look-ahead / carry-sellect /  BK adder achitecture?

 

  Thanks.

 

Below is the timing report:

 

--------------------------------------------------------------------------------
Slack:                  -2.132ns (requirement - (data path - clock path skew + uncertainty))
  Source:               module_a/recon_eng_mode_FFd1 (FF)
  Destination:          module_a/hv_sum_13 (FF)
  Requirement:          10.090ns
  Data Path Delay:      11.951ns (Levels of Logic = 11)
  Clock Path Skew:      -0.271ns
  Source Clock:         sys_clk_s_t_OBUF rising at 0.000ns
  Destination Clock:    sys_clk_s_t_OBUF rising at 10.090ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: module_a/recon_eng_mode_FFd1 to module_a/hv_sum_13
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X39Y17.YQ      Tcko                  0.520       module_a/recon_eng_mode_FFd1
                                                                                    module_a/recon_eng_mode_FFd1
    SLICE_X37Y16.G4      net (fanout=41)       0.610   module_a/recon_eng_mode_FFd1
    SLICE_X37Y16.Y       Tilo                  0.556             module_a/chm_cb_y_15<1>
                                                                                    module_a/f_index_or00001
    SLICE_X37Y17.F2      net (fanout=4)        0.348    module_a/f_index_or0000
    SLICE_X37Y17.X       Tilo                  0.557            module_a/recon_eng_mode_FFd2
                                                                                    module_a/Madd_factor2_xor<2>11
    DSP48A_X1Y2.B2       net (fanout=1)        0.735   module_a/factor2<2>
    DSP48A_X1Y2.P1       Tdspdo_BP             4.481   module_a/Mmult_mult0000_mult0000/DSP48A
                                                                                     module_a/Mmult_mult0000_mult0000/DSP48A
    SLICE_X35Y14.G3      net (fanout=1)        0.750    module_a/mult0000_mult0000<1>
    SLICE_X35Y14.COUT    Topcyg                1.001   module_a/prow_b_param<5>
                                                                                     module_a/Maddsub_hv_sum_addsub0000_lut<1>
                                                                                     module_a/Maddsub_hv_sum_addsub0000_cy<1>
    SLICE_X35Y15.CIN     net (fanout=1)        0.000    module_a/Maddsub_hv_sum_addsub0000_cy<1>
    SLICE_X35Y15.COUT    Tbyp                  0.129     module_a/intra_mode_data_a2<1>
                                                                                     module_a/Maddsub_hv_sum_addsub0000_cy<2>
                                                                                     module_a/Maddsub_hv_sum_addsub0000_cy<3>
    SLICE_X35Y16.CIN     net (fanout=1)        0.000    module_a/Maddsub_hv_sum_addsub0000_cy<3>
    SLICE_X35Y16.COUT    Tbyp                  0.129      module_a/hv_sum_addsub0000<4>
                                                                                     module_a/Maddsub_hv_sum_addsub0000_cy<4>
                                                                                     module_a/Maddsub_hv_sum_addsub0000_cy<5>
    SLICE_X35Y17.CIN     net (fanout=1)        0.000    module_a/Maddsub_hv_sum_addsub0000_cy<5>
    SLICE_X35Y17.COUT    Tbyp                  0.129     module_a/hv_sum_addsub0000<6>
                                                                                     module_a/Maddsub_hv_sum_addsub0000_cy<6>
                                                                                     module_a/Maddsub_hv_sum_addsub0000_cy<7>
    SLICE_X35Y18.CIN     net (fanout=1)        0.000    module_a/Maddsub_hv_sum_addsub0000_cy<7>
    SLICE_X35Y18.COUT    Tbyp                  0.129     module_a/hv_sum_addsub0000<8>
                                                                                     module_a/Maddsub_hv_sum_addsub0000_cy<8>
                                                                                     module_a/Maddsub_hv_sum_addsub0000_cy<9>
    SLICE_X35Y19.CIN     net (fanout=1)        0.000    module_a/Maddsub_hv_sum_addsub0000_cy<9>
    SLICE_X35Y19.COUT    Tbyp                  0.129     module_a/hv_sum_addsub0000<10>
                                                                                     module_a/Maddsub_hv_sum_addsub0000_cy<10>
                                                                                     module_a/Maddsub_hv_sum_addsub0000_cy<11>
    SLICE_X35Y20.CIN     net (fanout=1)        0.000    module_a/Maddsub_hv_sum_addsub0000_cy<11>
    SLICE_X35Y20.Y       Tciny                 0.658           module_a/hv_sum_addsub0000<12>
                                                                                      module_a/Maddsub_hv_sum_addsub0000_cy<12>
                                                                                     module_a/Maddsub_hv_sum_addsub0000_xor<13>
    SLICE_X35Y22.G4      net (fanout=1)        0.266    module_a/hv_sum_addsub0000<13>
    SLICE_X35Y22.CLK     Tgck                  0.824        module_a/hv_sum<13>
                                                                                     module_a/hv_sum_addsub0000<13>_rt
                                                                                     module_a/hv_sum_mux0000<13>_f5
                                                                                     module_a/hv_sum_13
    -------------------------------------------------  ---------------------------
    Total                                     11.951ns (9.242ns logic, 2.709ns route)
                                                       (77.3% logic, 22.7% route)

 

Message Edited by yangyuf1 on 07-28-2009 02:49 AM
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