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Visitor
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Registered: ‎10-21-2008

How to make XST synthesis an ADDER to a fast architesture?

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Hi:

  I have a problem with the XST synthesis tool.

  There is a critical paht in my design. This path include a 13 bits adder. From the timing report, it seems that XST use carry-ripple architecture to implemnet this function. How to force XST to use a high speed ADDER architecture to implement this function, such as carry-look-ahead / carry-sellect /  BK adder achitecture?

 

  Thanks.

 

Below is the timing report:

 

--------------------------------------------------------------------------------
Slack:                  -2.132ns (requirement - (data path - clock path skew + uncertainty))
  Source:               module_a/recon_eng_mode_FFd1 (FF)
  Destination:          module_a/hv_sum_13 (FF)
  Requirement:          10.090ns
  Data Path Delay:      11.951ns (Levels of Logic = 11)
  Clock Path Skew:      -0.271ns
  Source Clock:         sys_clk_s_t_OBUF rising at 0.000ns
  Destination Clock:    sys_clk_s_t_OBUF rising at 10.090ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: module_a/recon_eng_mode_FFd1 to module_a/hv_sum_13
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X39Y17.YQ      Tcko                  0.520       module_a/recon_eng_mode_FFd1
                                                                                    module_a/recon_eng_mode_FFd1
    SLICE_X37Y16.G4      net (fanout=41)       0.610   module_a/recon_eng_mode_FFd1
    SLICE_X37Y16.Y       Tilo                  0.556             module_a/chm_cb_y_15<1>
                                                                                    module_a/f_index_or00001
    SLICE_X37Y17.F2      net (fanout=4)        0.348    module_a/f_index_or0000
    SLICE_X37Y17.X       Tilo                  0.557            module_a/recon_eng_mode_FFd2
                                                                                    module_a/Madd_factor2_xor<2>11
    DSP48A_X1Y2.B2       net (fanout=1)        0.735   module_a/factor2<2>
    DSP48A_X1Y2.P1       Tdspdo_BP             4.481   module_a/Mmult_mult0000_mult0000/DSP48A
                                                                                     module_a/Mmult_mult0000_mult0000/DSP48A
    SLICE_X35Y14.G3      net (fanout=1)        0.750    module_a/mult0000_mult0000<1>
    SLICE_X35Y14.COUT    Topcyg                1.001   module_a/prow_b_param<5>
                                                                                     module_a/Maddsub_hv_sum_addsub0000_lut<1>
                                                                                     module_a/Maddsub_hv_sum_addsub0000_cy<1>
    SLICE_X35Y15.CIN     net (fanout=1)        0.000    module_a/Maddsub_hv_sum_addsub0000_cy<1>
    SLICE_X35Y15.COUT    Tbyp                  0.129     module_a/intra_mode_data_a2<1>
                                                                                     module_a/Maddsub_hv_sum_addsub0000_cy<2>
                                                                                     module_a/Maddsub_hv_sum_addsub0000_cy<3>
    SLICE_X35Y16.CIN     net (fanout=1)        0.000    module_a/Maddsub_hv_sum_addsub0000_cy<3>
    SLICE_X35Y16.COUT    Tbyp                  0.129      module_a/hv_sum_addsub0000<4>
                                                                                     module_a/Maddsub_hv_sum_addsub0000_cy<4>
                                                                                     module_a/Maddsub_hv_sum_addsub0000_cy<5>
    SLICE_X35Y17.CIN     net (fanout=1)        0.000    module_a/Maddsub_hv_sum_addsub0000_cy<5>
    SLICE_X35Y17.COUT    Tbyp                  0.129     module_a/hv_sum_addsub0000<6>
                                                                                     module_a/Maddsub_hv_sum_addsub0000_cy<6>
                                                                                     module_a/Maddsub_hv_sum_addsub0000_cy<7>
    SLICE_X35Y18.CIN     net (fanout=1)        0.000    module_a/Maddsub_hv_sum_addsub0000_cy<7>
    SLICE_X35Y18.COUT    Tbyp                  0.129     module_a/hv_sum_addsub0000<8>
                                                                                     module_a/Maddsub_hv_sum_addsub0000_cy<8>
                                                                                     module_a/Maddsub_hv_sum_addsub0000_cy<9>
    SLICE_X35Y19.CIN     net (fanout=1)        0.000    module_a/Maddsub_hv_sum_addsub0000_cy<9>
    SLICE_X35Y19.COUT    Tbyp                  0.129     module_a/hv_sum_addsub0000<10>
                                                                                     module_a/Maddsub_hv_sum_addsub0000_cy<10>
                                                                                     module_a/Maddsub_hv_sum_addsub0000_cy<11>
    SLICE_X35Y20.CIN     net (fanout=1)        0.000    module_a/Maddsub_hv_sum_addsub0000_cy<11>
    SLICE_X35Y20.Y       Tciny                 0.658           module_a/hv_sum_addsub0000<12>
                                                                                      module_a/Maddsub_hv_sum_addsub0000_cy<12>
                                                                                     module_a/Maddsub_hv_sum_addsub0000_xor<13>
    SLICE_X35Y22.G4      net (fanout=1)        0.266    module_a/hv_sum_addsub0000<13>
    SLICE_X35Y22.CLK     Tgck                  0.824        module_a/hv_sum<13>
                                                                                     module_a/hv_sum_addsub0000<13>_rt
                                                                                     module_a/hv_sum_mux0000<13>_f5
                                                                                     module_a/hv_sum_13
    -------------------------------------------------  ---------------------------
    Total                                     11.951ns (9.242ns logic, 2.709ns route)
                                                       (77.3% logic, 22.7% route)

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Explorer
Explorer
10,762 Views
Registered: ‎07-27-2009

Re: How to make XST synthesis an ADDER to a fast architesture?

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yangyuf1,

 

To clarify: the only time I ever instanced it manually was for some very timing critical DSP section to have very fine grained control over all the options the DSP slice provides.

 

For your case, you might get lucky by using the USE_DSP48 synthesis constraint/xst parameter/vhdl attribute/... [google it, or have a look at the xilinx docs]. For some reasons, by default XST will only try to map multipliers to DSP slices. Subsequent adders will _not_ be automatically mapped. Pretty annoying that they don't recognize the fact that they already inferred the mult and as a result they can absorb the adder into the DSP slice.

 

View solution in original post

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Teacher
Teacher
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Registered: ‎07-09-2009

Re: How to make XST synthesis an ADDER to a fast architesture?

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Whats your UCF / timming constraints ?

 

 what is your code ? I assume your inferring the adders, not instantiating.

 

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Explorer
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Registered: ‎07-27-2009

Re: How to make XST synthesis an ADDER to a fast architesture?

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Note how there is a path through a DSP slice taking 4+ns. It seems to be part of a multiply operation, so you should check if you have an adder in series with a multiplier. Adding a pipeline stage will help here. Alternatively you could instance the DSP directly and use the adders in there but that is probably more cumbersome.

 

Providing some HDL would help.

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Teacher
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Registered: ‎07-09-2009

Re: How to make XST synthesis an ADDER to a fast architesture?

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Well spotted woutersj, I'm kicking myself for not spotting that DSP48....

 

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Explorer
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Registered: ‎07-27-2009

Re: How to make XST synthesis an ADDER to a fast architesture?

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Yeah... I've had the pleasure (slightly sarcatic here) of optimizing a few designs for high speed operation on multiple generations of Xilinx devices so reverse engineering timing reports from a variety of tools has become a bit of a hobby.

 

Anyway, hope this helps the author as this kind of thing can be baffling at times.

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Visitor
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Registered: ‎10-21-2008

Re: How to make XST synthesis an ADDER to a fast architesture?

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Thanks very much of your reply and kindly help.

 

The RTl code will some thing like:

 hv_sum = (a[7:0] * b[7:0] ) + c[12:0]

 

So there is a DSP48 module to do the multiply(inferred,not instanted).  And some luts to do the adder function.

 

    From the reply of woutersj, it seems that I need instance the DSP48 module and use both the multiply and adder function in itself. This is of cause a good solution. But when I need put this code to ASIC synthesis, I need change the RTL code, this is what I don't want. I want to put the work of architeture and cell select to synthesis tool, not manually instantion.

 

    So, how can I force xilinx systnesis tool use both the multiply and adder function within the DSP48 hard cell. Or how can I force xilinx synthesis tool synthesis this adder function using a fast architecture, such as carry-look-ahead / carry-sellect architecture?

  Thanks.

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Explorer
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10,763 Views
Registered: ‎07-27-2009

Re: How to make XST synthesis an ADDER to a fast architesture?

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yangyuf1,

 

To clarify: the only time I ever instanced it manually was for some very timing critical DSP section to have very fine grained control over all the options the DSP slice provides.

 

For your case, you might get lucky by using the USE_DSP48 synthesis constraint/xst parameter/vhdl attribute/... [google it, or have a look at the xilinx docs]. For some reasons, by default XST will only try to map multipliers to DSP slices. Subsequent adders will _not_ be automatically mapped. Pretty annoying that they don't recognize the fact that they already inferred the mult and as a result they can absorb the adder into the DSP slice.

 

View solution in original post

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Teacher
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Registered: ‎07-09-2009

Re: How to make XST synthesis an ADDER to a fast architesture?

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this might work,

 

ftp://ftp.xilinx.com/pub/documentation/misc/dsp48_inference.pdf

 

'hidden' away on the xilinx site are various examples of how to inferr various bits, 

 

 

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Visitor
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Registered: ‎10-21-2008

Re: How to make XST synthesis an ADDER to a fast architesture?

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woutersj :

 

  Thanks very much for your reply.

  Get the point.

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