How to prevent implementation of shift registers in BRAM

[rty]

Hello.

I have a project in Vivado 2016.4 which contains the verilog file with shift registers that I want to be implemented with SRL primitives.

I am using such directive in the file:

(* shreg_extract = "yes" *)module

It works fine until I set the synthesis directive = AreaOptimized_high.

In that case my shift registers begin to be implemented as BRAM.

How can I prevent implementation of my shift registers as BRAM? Is it possible to use some synthesis directive?

Or the only way is to set synthesis directive = AreaOptimized_medium?

Thank you in advance for answers.

[thakurr · Accepted solution]

Hi @rty

Try using SRL_STYLE attribute but please note that this attribute can be applied only on the signals and has to declared in the RTL only. Refer below link, page 58 for more information on this:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_3/ug901-vivado-synthesis.pdf

Regards

Rohit

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[rty]

This helped me, thank you.