03-26-2020 01:23 PM
According to AR# 11231, I put the following pragma line above my module definition in a verilog file and intended to keep the ports not being ptimized out:
//pragma attribute comp_inst hierarchy "preserve";
module my_module (.....
I am using precision to synthesize my verilog design. But it seems not making any differences. In the synthesized file, the ports of my_module still not present. Does anyone know what I might have been doing wrong?
Is there any other ways to keep ports or wires in the syhthesized result so I can pull them out to a debug core? Thanks.
03-26-2020 07:40 PM
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03-29-2020 07:05 AM