cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Participant
Participant
343 Views
Registered: ‎01-31-2020

How to retain module input/out ports and not being optimized out using precision sythesis?

According to  AR# 11231,  I put the following pragma line above my module definition in a verilog file and intended to keep the ports not being ptimized out:

//pragma attribute comp_inst hierarchy "preserve";
module my_module (.....

I am using precision to synthesize my verilog design. But it seems not making any differences. In the synthesized file, the ports of my_module still not present. Does anyone know what I might have been doing wrong?

Is there any other ways to keep ports or wires in the syhthesized result so I can pull them out to a debug core? Thanks.

0 Kudos
5 Replies
Highlighted
Xilinx Employee
Xilinx Employee
311 Views
Registered: ‎05-22-2018

Re: How to retain module input/out ports and not being optimized out using precision sythesis?

Hi @zhua ,

Try to put KEEP_HIERARCHY property in constraint file. Check page no.137 of below link:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/cgd.pdf

Thanks,

Raj

Highlighted
Participant
Participant
275 Views
Registered: ‎01-31-2020

Re: How to retain module input/out ports and not being optimized out using precision sythesis?

Hi Raj,
Is this the right syntax?
(* KEEP_HIERARCHY = "{TRUE}" *)
module my_module (......

I am running precision now and see how it goes.
Thanks,
Zhi
0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
246 Views
Registered: ‎05-22-2018

Re: How to retain module input/out ports and not being optimized out using precision sythesis?

Hi @zhua ,

Instead in RTL, apply it in UCF:

INST “instance_name ” KEEP_HIERARCHY={TRUE|FALSE};

Thanks,

Raj

0 Kudos
Highlighted
Participant
Participant
204 Views
Registered: ‎01-31-2020

Re: How to retain module input/out ports and not being optimized out using precision sythesis?

Thanks Raj. I put "(* keep_hierarchy = "yes" *)" at the front of the module instantiation. It see the hierary is kept in the sythesized file now. But the ports are still optimized out. I tried to add "(* S = YES *)" at the front of module input/output signal definiton. Precision did not like it and gave an error.
0 Kudos
Highlighted
Moderator
Moderator
183 Views
Registered: ‎07-21-2014

Re: How to retain module input/out ports and not being optimized out using precision sythesis?

@zhua 

Looks like you are using 3rd party tools, can you please use the 3rd party's forums to get details on its usage.   

Thanks
Anusheel 

0 Kudos