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Observer
Observer
3,709 Views
Registered: ‎02-06-2017

How to synthesize without optimization in vivado?

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Hello Guys

 

I have synthesized logic that have a buffer to use delay.

 

For example,

 

module buffer(output out, input in);

buf b1(out, in);

endmodule

 

or 

 

module nbuffer(output out, input in);

not n1(w1, in);

not n2(out, w1);

endmodule

 

But buffer converted to wire in optimization.

 

I want buffers to be kept. 

 

How to synthesize without optimization in vivado?

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Moderator
Moderator
6,731 Views
Registered: ‎07-21-2014

@grimlk

 

Try using DONT_TOUCH attribute to preserve these cells: (* DONT_TOUCH = "yes" *)  wire w1;

 

 

Thanks,
Anusheel
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Moderator
Moderator
6,732 Views
Registered: ‎07-21-2014

@grimlk

 

Try using DONT_TOUCH attribute to preserve these cells: (* DONT_TOUCH = "yes" *)  wire w1;

 

 

Thanks,
Anusheel
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View solution in original post

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Observer
Observer
3,703 Views
Registered: ‎09-15-2016

Hi@@grimlk,

 

Please refer UG-901, page 45 and see if it helps.
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_4/ug901-vivado-synthesis.pdf

 

Thanks,

Asit

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