UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Newbie sai777
Newbie
134 Views
Registered: ‎09-11-2019

How to tell the vivado not to use particular region in FPGA

Hi ,

Is tere any constraint ,so that my logic will not placed any particular region of the FPGA. 

We have the constraints to keep the logic in particular region,like this way is there any constraint not to use some region of the FPGA.

 

Thanks in adavance,

Sai

0 Kudos
2 Replies
Moderator
Moderator
119 Views
Registered: ‎11-04-2010

Re: How to tell the vivado not to use particular region in FPGA

Hi, @sai777 ,

Do you mean all the logic cannot be placed in the specific region?

You can try to set the prohibit property to avoid logic placing.

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Moderator
Moderator
89 Views
Registered: ‎11-04-2010

Re: How to tell the vivado not to use particular region in FPGA

Hi, @sai777 ,

Another method for you to try:

1. Create an empty pblock which contains the region you don't want to place any logic.
2. Set the pblock as Placement excluded to avoid the logic enter the specific region.

Example constraints:

create_pblock pblock_1
resize_pblock pblock_1 -add CLOCKREGION_X1Y3:CLOCKREGION_X1Y3
set_property EXCLUDE_PLACEMENT 1 [get_pblocks pblock_1]

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos