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greatmaverick
Explorer
Explorer
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Registered: ‎04-06-2017

How to use multiple CPU cores during synthesis?

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I use ISE to develop FPGA project. I feel synthesis take much time for my particular application. How to use multiple CPU cores during synthesis?  And how to do that during implementation?

Thank you

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dm78
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Registered: ‎03-15-2012

You may be able to "backport" the OOC from vivado to ISE.

You have to divide your design into some jucy parts, synthesis them into netlists (ngc) and let them merge (during synthesis or translate step). These netlists may can be generated in parallel and can be cached.

PS: This is like a Microblaze via EDK gets into the design.

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dm78
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Adventurer
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Registered: ‎03-15-2012

you can add "-mt on" on most of the tools. But the benefit is quite low according to my experiences. The ISE tools do not really use multithreading.

That's why i use a CORE-i7/9 with only a few cores but high speed and not an AMD Threadripper for example.

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greatmaverick
Explorer
Explorer
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Registered: ‎04-06-2017
The default synthesis tool in ISE does not have -mt on option. Thank you
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dm78
Adventurer
Adventurer
1,450 Views
Registered: ‎03-15-2012

You may be able to "backport" the OOC from vivado to ISE.

You have to divide your design into some jucy parts, synthesis them into netlists (ngc) and let them merge (during synthesis or translate step). These netlists may can be generated in parallel and can be cached.

PS: This is like a Microblaze via EDK gets into the design.

View solution in original post

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