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Visitor
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Registered: ‎01-13-2010

I get warning Xst:2677 - Node <s12_reg4_12> of sequential type is unconnected in block <U31>. whenever i synthesize this module.

It is creating problems.Iget hundreds of such warnings .I don't know how to correct

 here is the code

module mult12sx8u(
                  clk,
                  n1,
                  n2,
                  dctq
                 ) ;

input                   clk ;

input  [11:0]           n1 ;
input  [7:0]            n2 ;
/*output [19:0]           dctq ;*/

wire                    n1orn2z ;

wire   [11:0]           p1 ;
wire   [11:0]           p2 ;
wire   [11:0]           p3 ;
wire   [11:0]           p4 ;
wire   [11:0]           p5 ;
wire   [11:0]           p6 ;
wire   [11:0]           p7 ;
wire   [11:0]           p8 ;

wire   [7:0]            s11a ;
wire   [7:0]            s12a ;
wire   [7:0]            s13a ;
wire   [7:0]            s14a ;

wire   [5:0]            s11b ;
wire   [5:0]            s12b ;
wire   [5:0]            s13b ;
wire   [5:0]            s14b ;

wire   [13:0]           s11;
wire   [13:0]           s12 ;
wire   [13:0]           s13 ;
wire   [13:0]           s14 ;

wire   [8:0]            s21a ;
wire   [8:0]            s22a ;

wire   [6:0]            s21b ;
wire   [6:0]            s22b ;

wire   [15:0]           s21 ;
wire   [15:0]           s22 ;

wire   [9:0]            s31a ;
wire   [7:0]            s31b ;
wire   [18:0]           s31 ;

wire                    res_sign ;

wire   [19:0]           res ;

reg    [11:0]           n1_mag ;
reg    [7:0]            n2_mag ;

reg    [11:0]           p1_reg1 ;
reg    [11:0]           p2_reg1 ;
reg    [11:0]           p3_reg1 ;
reg    [11:0]           p4_reg1 ;
reg    [11:0]           p5_reg1 ;
reg    [11:0]           p6_reg1 ;
reg    [11:0]           p7_reg1 ;
reg    [11:0]           p8_reg1 ;

reg    [7:0]            s11a_reg2 ;
reg    [7:0]            s12a_reg2 ;
reg    [7:0]            s13a_reg2 ;
reg    [7:0]            s14a_reg2 ;

reg                     n1_reg1;
reg                     n1_reg2;
reg                     n1_reg3;
reg                     n1_reg4;
reg                     n1_reg5;
reg                     n1_reg6;
reg                     n1_reg7;

reg                     n2_reg1;
reg                     n2_reg2;
reg                     n2_reg3;
reg                     n2_reg4;
reg                     n2_reg5;
reg                     n2_reg6;
reg                     n2_reg7;

reg                n1orn2z_reg1 ;
reg                n1orn2z_reg2 ;
reg                n1orn2z_reg3 ;
reg                n1orn2z_reg4 ;
reg                n1orn2z_reg5 ;
reg                n1orn2z_reg6 ;
reg                n1orn2z_reg7 ;

reg    [11:0]           p1_reg2 ;
reg    [11:0]           p2_reg2 ;
reg    [11:0]           p3_reg2 ;
reg    [11:0]           p4_reg2 ;
reg    [11:0]           p5_reg2 ;
reg    [11:0]           p6_reg2 ;
reg    [11:0]           p7_reg2 ;
reg    [11:0]           p8_reg2 ;

reg    [13:0]           s11_reg3 ;
reg    [13:0]           s12_reg3 ;
reg    [13:0]           s13_reg3 ;
reg    [13:0]           s14_reg3 ;

reg    [13:0]           s11_reg4 ;
 
reg    [13:0]           s12_reg4  ;
reg    [13:0]           s13_reg4  ;
reg    [13:0]           s14_reg4  ;

reg    [8:0]            s21a_reg4 ;
reg    [8:0]            s22a_reg4 ;

reg    [15:0]           s21_reg5 ;
reg    [15:0]           s22_reg5 ;

reg    [15:0]           s21_reg6 ;
reg    [15:0]           s22_reg6 ;

reg    [9:0]            s31a_reg6 ;

reg    [18:0]           s31_reg7 ;

reg    [19:0]           result ;
output [15:0] dctq;

always @(n1)

begin

if(n1[11] == 1'b0)
n1_mag = n1[11:0];
else
n1_mag = ~n1[11:0] + 1;   // Evaluate twos complement.

end


always @(n2)
begin

if(n2[7] == 1'b0)
n2_mag = n2[7:0];
else
n2_mag = ~n2[7:0] + 1;    // Evaluate twos complement.

end

assign n1orn2z = ((n1 == 12'b0)||(n2 == 7'b0)) ? 1'b1:1'b0;
                                // If n1 or n2 is zero, make final result +0.

assign p1 = n1_mag[11:0] & {11{n2_mag[0]}}; // Compute the partial products
assign p2 = n1_mag[11:0] & {11{n2_mag[1]}}; // n1 multiplied by n2 bit '0', etc.
assign p3 = n1_mag[11:0] & {11{n2_mag[2]}};
assign p4 = n1_mag[11:0] & {11{n2_mag[3]}};
assign p5 = n1_mag[11:0] & {11{n2_mag[4]}};
assign p6 = n1_mag[11:0] & {11{n2_mag[5]}};
assign p7 = n1_mag[11:0] & {11{n2_mag[6]}};
assign p8 = n1_mag[11:0] & {11{n2_mag[7]}};


always @ (posedge clk)  // This is the first pipeline register, clk (1).

begin

p1_reg1 <= p1;
p2_reg1 <= p2;
p3_reg1 <= p3;
p4_reg1 <= p4;
p5_reg1 <= p5;
p6_reg1 <= p6;
p7_reg1 <= p7;
p8_reg1 <= p8;

n1_reg1      <= n1[11];
n2_reg1      <= n2[7];
n1orn2z_reg1 <= n1orn2z;

end

//p1_reg1, etc. means p1, etc. are registered after positive edge of clk (1), clk (2), etc.


assign s11a[7:0] = p1_reg1[7:1] + p2_reg1[6:0]; // LSB is added here.
assign s12a[7:0] = p3_reg1[7:1] + p4_reg1[6:0]; // Note that the left shifts are taken care
assign s13a[7:0] = p5_reg1[7:1] + p6_reg1[6:0]; // for p1, p3, p5 and p7.
assign s14a[7:0] = p7_reg1[7:1] + p8_reg1[6:0]; // p1_reg1[0], etc. will be
                                                // processed at the clk (2).
                                                // s11a[6], etc. are the carry bits.

always @ (posedge clk)   // This is the second pipeline register, clk (2).

begin

s11a_reg2 <= s11a;   // Store LSB partial sums.
s12a_reg2 <= s12a;
s13a_reg2 <= s13a;
s14a_reg2 <= s14a;

p1_reg2[11:8] <= p1_reg1[11:8]; // Store MSB of partial products.
p2_reg2[11:7] <= p2_reg1[11:7];
p3_reg2[11:8] <= p3_reg1[11:8];
p4_reg2[11:7] <= p4_reg1[11:7];
p5_reg2[11:8] <= p5_reg1[11:8];
p6_reg2[11:7] <= p6_reg1[11:7];
p7_reg2[11:8] <= p7_reg1[11:8];
p8_reg2[11:7] <= p8_reg1[11:7];

p1_reg2[0] <= p1_reg1[0];  // Store '0' th bit since
p3_reg2[0] <= p3_reg1[0];  // it is not yet processed.
p5_reg2[0] <= p5_reg1[0];
p7_reg2[0] <= p7_reg1[0];

n1_reg2      <= n1_reg1;  // Also store sign bits and zero status.
n2_reg2      <= n2_reg1;
n1orn2z_reg2 <= n1orn2z_reg1;

end


// MSB is added here along with carry.

assign s11b[5:0] = {1'b0, p1_reg2[11:8]} + p2_reg2[11:7] + s11a_reg2[7];
assign s12b[5:0] = {1'b0, p3_reg2[11:8]} + p4_reg2[11:7] + s12a_reg2[7];
assign s13b[5:0] = {1'b0, p5_reg2[11:8]} + p6_reg2[11:7] + s13a_reg2[7];
assign s14b[5:0] = {1'b0, p7_reg2[11:8]} + p8_reg2[11:7] + s14a_reg2[7];

// MSBs & LSBs are concatenated here.

assign s11[13:0] = {s11b, s11a_reg2[6:0], p1_reg2[0]} ;  // MSB, LSB, '0' th bit
assign s12[13:0] = {s12b, s12a_reg2[6:0], p3_reg2[0]} ;  // respectively.
assign s13[13:0] = {s13b, s13a_reg2[6:0], p5_reg2[0]} ;
assign s14[13:0] = {s14b, s14a_reg2[6:0], p7_reg2[0]} ;


always @ (posedge clk)  // This is the third pipeline register, clk (3).
     // First stage results.
begin

s11_reg3 <= s11;   // Store for further processing.
s12_reg3 <= s12;
s13_reg3 <= s13;
s14_reg3 <= s14;

n1_reg3      <= n1_reg2;
n2_reg3      <= n2_reg2;
n1orn2z_reg3 <= n1orn2z_reg2;

end


assign s21a[8:0] = s11_reg3[9:2] + s12_reg3[7:0]; // LSB sum, 2nd stage.
assign s22a[8:0] = s13_reg3[9:2] + s14_reg3[7:0]; // s21a[7] & s22a[7] are the carry.


always @ (posedge clk)   // This is the fourth pipeline register, clk (4).

begin

s11_reg4[13:10] <= s11_reg3[13:10];  // Store bits not yet processed.
s11_reg4[1:0]  <= s11_reg3[1:0];
s12_reg4[13:8] <= s12_reg3[13:8];
s13_reg4[13:10] <= s13_reg3[13:10];
s13_reg4[1:0]  <= s13_reg3[1:0];
s14_reg4[13:8] <= s14_reg3[13:8];

s21a_reg4 <= s21a;   // Store LSB, second stage partial sums.
s22a_reg4 <= s22a;

n1_reg4      <= n1_reg3;
n2_reg4      <= n2_reg3;
n1orn2z_reg4 <= n1orn2z_reg3;

end


// Add second stage MSBs with carry.

assign s21b[6:0] = {2'b0, s11_reg4[13:10]} + s12_reg4[13:8] + s21a_reg4[8]; 
assign s22b[6:0] = {2'b0, s13_reg4[13:10]} + s14_reg4[13:8] + s22a_reg4[8];

assign s21[15:0] = {s21b[5:0], s21a_reg4[7:0], s11_reg4[1:0]} ; // {MSB, LSB, [1:0]}

// Result will never effect s21b[6], which is always 0.

assign s22[15:0] = {s22b[6:0], s22a_reg4[6:0], s13_reg4[1:0]} ;


always @ (posedge clk)   // This is the fifth pipeline register, clk (5).

begin

s21_reg5 <= s21;    // Store for further processing.
s22_reg5 <= s22;

n1_reg5      <= n1_reg4;
n2_reg5      <= n2_reg4;
n1orn2z_reg5 <= n1orn2z_reg4;

end


assign s31a[9:0] = s21_reg5[12:4] + s22_reg5[8:0];

       //  3rd stage LSB computed here.


always @ (posedge clk)// This is the sixth pipeline register, clk (6).

begin

s21_reg6[15:13]<= s21_reg5[15:13];  // Preserve MSB.
s22_reg6[15:9] <= s22_reg5[15:9];
s21_reg6[3:0]  <= s21_reg5[3:0];
s31a_reg6      <= s31a;    //3rd stage LSB registered here.

n1_reg6      <= n1_reg5;
n2_reg6      <= n2_reg5;
n1orn2z_reg6 <= n1orn2z_reg5;

end

 

assign s31b[7:0] = {4'b0, s21_reg6[15:13]} + s22_reg6[15:9] + s31a_reg6[9];

       // 3rd stage MSB computed here.

assign s31[18:0] = {s31b[5:0], s31a_reg6[8:0], s21_reg6[3:0]} ;

// Put MSB, LSB and [3:0] bits together.

// Note that the 3rd stage result will never effect s31b[6:5], which is always 0.


always @ (posedge clk)   // This is the seventh pipeline register, clk (7).

begin

n1_reg7      <= n1_reg6;  // Store intermediate results.
n2_reg7      <= n2_reg6;
s31_reg7      <= s31;
n1orn2z_reg7 <= n1orn2z_reg6;

end


assign res_sign = n1_reg7^n2_reg7; // '1' means a -ve no.

assign res[19:0] = (res_sign ) ? {1'b1, (~s31_reg7 + 1'b1)}:{1'b0, s31_reg7};


always @ (posedge clk)         // This is the eighth pipeline register, clk (8).

begin

if (n1orn2z_reg7 == 1'b1)
result[19:0] <= 19'b0;
else
result[19:0] <= res;    // This is the final result (product of two numbers)
         // in twos complement.
end
assign dctq=result/16;


endmodule
I also get a warning Xst:1710 - FF/Latch  <6> (without init value) has a constant value of 0 in block <p8_reg1>.

not pertaining to this code

kindly reply

thanks

charan

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Professor
Professor
9,714 Views
Registered: ‎08-14-2007

Re: I get warning Xst:2677 - Node <s12_reg4_12> of sequential type is unconnected in block <U31>. whenever i synthesize this module.

The warning says you're not using some bits of a vector.  Did you

try to simulate this code to see what is happening?

By the way, the complaint is about bit 12, but it seems there are a

number of bits that are never assigned, unless you didn't post

all of the code.  If you don't use the low bits of a vector,

you can define the vector like

reg [13:8] s12_reg4;

 

There's nothing that says a vector needs to have a bit zero.  If you

only define the bits you use, then the warnings should represent

real problems in the design.  If hyou have lots of unused bits you

will have to pore through reams of warnings to find the real issue

with the design.  By the way, the warning message may not

indicate a real problem.  That's why you need to simulate to

see where your issues are.  Often a perfectly working design

can have hundreds of warnings during synthesis.  It's up to you

to either use cleaner coding or to ensure that the warnings can

be ignored.

 

HTH,

Gabor

-- Gabor
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Visitor
Visitor
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Registered: ‎01-13-2010

Re: I get warning Xst:2677 - Node <s12_reg4_12> of sequential type is unconnected in block <U31>. whenever i synthesize this module.

thanks for your reply.

I have given entire module and those registers are used only in this module.The simulation works correctly.in addition I've a situation where in a register [13:0] i will be using the upper 3 bits from msb and lower 8 bits from lsb,while other bits are unused.how can i solve this, can i assign any initial value and get rid of the warning?

do you have any information of 2nd warning Xst 1710?

Thank you

charan 

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Professor
Professor
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Registered: ‎08-14-2007

Re: I get warning Xst:2677 - Node <s12_reg4_12> of sequential type is unconnected in block <U31>. whenever i synthesize this module.

Well, the first thing I can say is you don't need to "solve" all of your

warnings, as warnings are not errors.  Sometimes you just have to ignore them.

The important thing is to understand what your code does so you can determine

if the warnings represent a real problem or not.  For example warning 1710 just

says that some bit(s) of a register don't change under all operating conditions.

This may in fact be correct given the application you're coding up.  In that case

you can ignore the message.

 

It's not possible to create a vector register with missing bits in its range.  So

if you want to avoid warnings when you don't use bits in the middle you need

to use more than one register definition, or else get used to ignoring some

warnings.  So for example if you had "reg [13:0] foo;" but don't use bits [9:8]

you could just ignore warnings about bits 9 and 8 or define instead:

reg [13:10] foo_h;

reg [7:0] foo_l;

and then use concatenation if necessary like:

frob <= {foo_h,2'b0,foo_l} + bar;

 

Personally I think that jumping through such hoops just to avoid a couple warnings

is counterproductive and leads to code that is hard to read.

 

HTH,

Gabor

-- Gabor
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Visitor
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Re: I get warning Xst:2677 - Node <s12_reg4_12> of sequential type is unconnected in block <U31>. whenever i synthesize this module.

Thanks again for your help

One thing I'm not clear ,is it  necessary that the processes implement design(synthesize ,translate) give a green signal if we want to dump this code into FPGA and warnings don't interfere.

other warnings i previously didn't mention was

WARNING:Xst:1710 - FF/Latch  <s12a_reg2_2> (without init value) has a constant value of 0 in block <U31>.

WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <p2_reg2_1> (without init value) has a constant value of 0 in block <U31>.

 

WARNING:Xst:1290 - Hierarchical block <u16> is unconnected in block <dctq>.


WARNING:Xst - Property "use_dsp48" is not applicable for this technology.
  kindly reply 
thank you
charan 

 

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Professor
Professor
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Re: I get warning Xst:2677 - Node <s12_reg4_12> of sequential type is unconnected in block <U31>. whenever i synthesize this module.

As long as you don't have any errors, you should be able to create a .bit file and load

the FPGA.  It is possible to get errors in the "generate programming file" process as

well, but this is less common.

-- Gabor
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Historian
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Registered: ‎02-25-2008

Re: I get warning Xst:2677 - Node <s12_reg4_12> of sequential type is unconnected in block <U31>. whenever i synthesize this module.


charan wrote:

Thanks again for your help

One thing I'm not clear ,is it  necessary that the processes implement design(synthesize ,translate) give a green signal if we want to dump this code into FPGA and warnings don't interfere.

other warnings i previously didn't mention was

WARNING:Xst:1710 - FF/Latch  <s12a_reg2_2> (without init value) has a constant value of 0 in block <U31>.


This is telling you that the signal s12a_reg2_2 is never initialized and is never assigned. This may or may not be a problem for your design, which is why it's flagged as a warning. You should investigate this to see why you get the warning.

 


WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <p2_reg2_1> (without init value) has a constant value of 0 in block <U31>.


This is likely a consequence of the previous warning. Since all of the stuff that drives p2_reg2_1 has been optimized to a constant 0, p2_reg2_1 itself is optimized to a constant 0. Again, this may or may not be a problem for your design.


WARNING:Xst:1290 - Hierarchical block <u16> is unconnected in block <dctq>.


This means that u16 is not used. Generally you see this when an entity's outputs don't drive anything in the larger design. Figure out why this is the case. If u16 is truly unused, delete it and the warning goes away.
 
WARNING:Xst - Property "use_dsp48" is not applicable for this technology.
  kindly reply 
 

This is one of Xilinx' patented Stupid Warnings. XST has a switch that tells it whether it should try to use DSP48 blocks to handle certain math operations or not. Regardless of this switch's setting, if the device architecture does not have DSP48s then you get this warning.

----------------------------Yes, I do this for a living.
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Re::Xst:1290 - Hierarchical block <u16> is unconnected in block <dctq>.

Thank  you very much,that will certainly help much.

But concerning to the warning XST:1290 ,block <u16> has been used it is a 8x8 multiplier and 8 similiar blocks are used .i don't know why this block in particular.All the ports are   matched . Is there any other reason for this.

thank you 

charan

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Professor
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Re: Re::Xst:1290 - Hierarchical block <u16> is unconnected in block <dctq>.

Not knowing where it is hooked up in your design, it's hard to say why <u16> is unconnected.

However here's a guess...

 

If you have a 32 by 32 multiplier and don't use the upper 32 bits of the result, there will be

a large unused portion of the multiplier.  Now if that multiplier was constructed by a number

of 8 x 8 multipliers there could easily be some 8 x 8 elements that are completely unused.

 

Here's an example of multiplication by hand that illustrates the issue:

 

        27

     x 49

  _____

        63  9 x 7

  +  180  9 x 20

  +  280 40 x 7

  +  800 40 x 20

______

    1323

 

Let's suppose that you only care about the two low order digits of the answer, "23".

Now also suppose you built this multiplier using one digit wide individual multipliers

as shown in the partial results.  Then you can see that:

1) It takes  4 of these one digit multipliers to implement the entire product.

2) The low two digits of the result only depend on the low two digits of each partial result.

3) The second and third of the partial results will always have only one output digit in the

     low two digits.

4) The  fourth of the partial results has no output digits in the lower two digits.

 

So the second and third one-digit multipliers are half-used and the last one unused

when you don't neet the upper two digits of the result.

 

Hopes this clears things up a little,

 

Gabor

-- Gabor
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