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thweight
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Registered: ‎08-07-2018

I2C for my ARTY S7

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Hi Everyone,

 

I am new to FPGA's and this is my first post. I hope this is in the right place.

 

I am trying to get i2c working on my ARTY board using (of course) the SDA and SCL pins and Vivado 2018.1 (64 bits).

 

All I want is to talk to one slave with no other masters. So I don't have to worry about making SCL open collector. But the SDA is another matter.

 

I have this code for writing to the inout sda port.

         if(l_sda_tx = '0') then

            sda <= '0';

         else

            sda <= 'Z';

         end if;

When I synthesize the program, I get a critical warning:

"[Synth 8-5799] Converted tricell instance 'U0i_0' to logic  ".

 

I googled this and learned that (with an older version of Vivado) I need to switch from "OOC" to "Global".

 

This is where I hit a brick wall. I found several explanations of how to do this but none seem to apply to my version of Vivado.

 

Thank you in advance for your help.

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gmarinkovic
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Registered: ‎01-09-2012

@thweight

 

I don't get where you are hitting the brick... with the ooc - > global or with the IO buffer?

As already showed by dpaul24 you see how to do this manually... or by Vivado automatically when you use the signal endings *_i, *_o and *_t...

In addition, although dpaul24 did not state it explicitly the line:

    I  => sda_o,  -- Bufferinput

means that sda_o is a constant and '0'.

 

Concerning your remark "...one slave with no other masters. So I don't have to worry about making SCL open collector..."

Be warned: There are I2C slaves which do clock stretching to delay a response... typically ADC based I2C components which need some time.Please check as well: https://www.i2c-bus.org/clock-stretching/

If your component drives a '1' (instead of a 'Z' which results due to the I2C pull-up resistor 'H') and your I2C slave stretches the clock by pulling it low -> you will go to the limit of your FPGA output driver. No a really nice behavior... will say, even if you do not care about clock stretching don't drive the SCK directly but by a open collector (iobuf).

 

Cheers

Goran

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3 Replies
dpaul24
Scholar
Scholar
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Registered: ‎08-07-2014

@thweight,

 

If the tri-state buffer connection of the SDA is worrying you the try using the Xilinx primitive IOBUF.

 

SDA_IOBUF_inst: IOBUF
    generic map(
    DRIVE      => 12,
    IOSTANDARD => "DEFAULT",
    SLEW       => "SLOW"
	)
    port map(
    O  => sda_i,  -- Buffer output
    IO => sda_io, -- Buffer inout port(connect directly to top-level port)
    I  => sda_o,  -- Bufferinput
    T  => sda_t   -- 3-state enable input,high=input,low=output
);

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gmarinkovic
Explorer
Explorer
2,535 Views
Registered: ‎01-09-2012

@thweight

 

I don't get where you are hitting the brick... with the ooc - > global or with the IO buffer?

As already showed by dpaul24 you see how to do this manually... or by Vivado automatically when you use the signal endings *_i, *_o and *_t...

In addition, although dpaul24 did not state it explicitly the line:

    I  => sda_o,  -- Bufferinput

means that sda_o is a constant and '0'.

 

Concerning your remark "...one slave with no other masters. So I don't have to worry about making SCL open collector..."

Be warned: There are I2C slaves which do clock stretching to delay a response... typically ADC based I2C components which need some time.Please check as well: https://www.i2c-bus.org/clock-stretching/

If your component drives a '1' (instead of a 'Z' which results due to the I2C pull-up resistor 'H') and your I2C slave stretches the clock by pulling it low -> you will go to the limit of your FPGA output driver. No a really nice behavior... will say, even if you do not care about clock stretching don't drive the SCK directly but by a open collector (iobuf).

 

Cheers

Goran

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thweight
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Registered: ‎08-07-2018
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