ICAP Watchdog: another use possible ? (not sure I should post this in this section)
As I understood: The watchdog timer wil wait for the SYNC signal "AA 99 55 66" to be received in the ICAP .... if not, it will reboot. But reboot will only happen when there are enough clock ticks on the ICAP, before the end of the bitstream has been found (succesfull init).
When looking to the bitfile hex- code: I find the watchdogtimer like : 31 e1 folowed by the value ff ff 33 21, witch should be the amount of ticks to wait before reboot/fallback. But since there is no more SYNC signal "AA 99 55 66" the WDT can trigger a reboot ... but this does not occure since the initialization is succesfull. Am I right whit this conclusion?
The question I had: Is it possible somehow to set the WDT and allow more clockticks on the ICAP, so that even after the init was succesfull the WDT is keeping counting? The idea would be to let the new implementation go in the FPGA and that it has to pass "AA 99 55 66" to the ICAP, so that it will not reboot. Doing that we can know that the new BIT file is "working" and not only "valid"