05-16-2020 04:11 PM
Configuring any Integrated Logic Analyzer on Vivado, it happens to me that the program does not create appropriate files and therefore the synthesis fails.
Here is a log:
*** Running vivado with args -log ila_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source ila_0.tcl ****** Vivado v2019.2 (64-bit) **** SW Build 2708876 on Wed Nov 6 21:39:14 MST 2019 **** IP Build 2700528 on Thu Nov 7 00:09:20 MST 2019 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. source ila_0.tcl -notrace WARNING: [Vivado 12-818] No files matched '/home/anton/fpga_adapted/fpga_adapted.srcs/sources_1/ip/ila_0/ila_v6_2/constraints/ila_impl.xdc' ERROR: [Common 17-55] 'set_property' expects at least one object. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. INFO: [Common 17-206] Exiting Vivado at Sun May 17 01:05:58 2020...
05-17-2020 01:11 AM - edited 05-17-2020 01:12 AM
05-17-2020 09:39 AM
05-17-2020 09:34 PM
Looks like the error is coming from ila_impl.xdc file.
Check correctly and see set_property commands are correctly written in it. The error message describes that set_property is not able to find the object mentioned with it.
If it is correct then share that xdc with us.