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Adventurer
Adventurer
4,053 Views
Registered: ‎03-28-2014

ILA causes unconnected pin on FIFO din

Hi All,

 

I am having a strange issue, where adding and ILA at a specific place in my design causes Critical Warnings during synthesis due to unconnected din pins on an instance of a FIFO. Without the ILA, these pins are connected just fine and the design works as expected.

 

The FIFO instance in question is in no way connected to the ILA; however the FIFO is instantiated twice and the "din" pins of the second instance are directly connected to the ILA but the second instance gives no warnings. Is there a work-around for the issue?

 

Thanks,

Dan

 

P.S. I'm using Vivado 2016.2

 

 

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3 Replies
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Xilinx Employee
Xilinx Employee
4,010 Views
Registered: ‎09-20-2012

Re: ILA causes unconnected pin on FIFO din

Hi @dcwhitehead

 

Can you open elaborated design and check if the Din pin of the IP is connected properly or not?

Thanks,
Deepika.
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Moderator
Moderator
3,994 Views
Registered: ‎07-01-2015

Re: ILA causes unconnected pin on FIFO din

Hi @dcwhitehead,

 

Are you seeing issue similar to https://www.xilinx.com/support/answers/65254.html ?

 

Thanks,
Arpan
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Adventurer
Adventurer
3,976 Views
Registered: ‎03-28-2014

Re: ILA causes unconnected pin on FIFO din

@vemulad Everything is connected correctly in the elaborated design. @arpansur I don't think that is the exact problem I am having.

 

Below is a striped down version of the code giving me trouble. The CDC_FIFO_SLOW_TO_FAST_inst FIFO instance is the one that gets the critical warning on DIN even though the ILA is connected to the DIN ports on the CDC_FIFO_FAST_TO_SLOW_inst FIFO instance.

 

 

	type BUS_TYPE is
	record
		SOF			:	std_logic;
		EOF			:	std_logic;
		VALID			:	std_logic;
		DAT			:	std_logic_vector(63 downto 0);
		NUM_BYTES		:	std_logic_vector( 2 downto 0);
	end record;
	
signal raw_slow_data,raw_fast_data	:	BUS_TYPE;
signal proc_fast_data,proc_slow_data	:	BUS_TYPE;

begin

CDC_FIFO_SLOW_TO_FAST_inst : entity work.CDC_FIFO
PORT MAP
(
	rst	=> reset,
	wr_clk	=> slow_clk,
	rd_clk	=> fast_clk,
	din(68)	=> raw_slow_data.SOF,
	din(67)	=> raw_slow_data.EOF,
	din(66 downto 64)	=> raw_slow_data.NUM_BYTES,
	din(63 downto  0)	=> raw_slow_data.DAT,
	wr_en	=> raw_slow_data.VALID,
	rd_en	=> '1',
	dout(68)		=> raw_fast_data.SOF,
	dout(67)		=> raw_fast_data.EOF,
	dout(66 downto 64)	=> raw_fast_data.NUM_BYTES,
	dout(63 downto  0)	=> raw_fast_data.DAT,
	full	=> open,
	empty	=> open,
	valid	=> raw_fast_data.VALID
);

-- raw_fast_data goes through significant amount of processing steps
-- and is written into DDR3 before being read out and converted to
-- proc_fast_data


PROC_ILA_inst : entity work.PROC_ILA
PORT MAP (
	clk => fast_clk,
	probe0(0) => proc_fast_data.SOF, 
	probe1(0) => proc_fast_data.EOF, 
	probe2(0) => proc_fast_data.VALID,
	probe3 => proc_fast_data.DAT
);

CDC_FIFO_FAST_TO_SLOW_inst : entity work.CDC_FIFO
PORT MAP
(
	rst	=> reset,
	wr_clk	=> fast_clk,
	rd_clk	=> slow_clk,
	din(68)				=> proc_fast_data.SOF,
	din(67)				=> proc_fast_data.EOF,
	din(66 downto 64)		=> proc_fast_data.NUM_BYTES,
	din(63 downto  0)		=> proc_fast_data.DAT,
	wr_en	=> proc_fast_data.VALID,
	rd_en	=> '1',
	dout(68)		=> proc_slow_data.SOF,
	dout(67)		=> proc_slow_data.EOF,
	dout(66 downto 64)	=> proc_slow_data.NUM_BYTES,
	dout(63 downto  0)	=> proc_slow_data.DAT,
	full	=> open,
	empty	=> open,
	valid	=> proc_slow_data.VALID
);

 

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