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Registered: ‎10-12-2016

IOB component usage in Synthesis and XDC file ?

Hi Friends, 

My Design using IOB's, In Laguage template I come across following constraints in synthesis ans xdc for IOB. Can anyone pls explain what are those for ? 

IOB_usage_post.PNGsynth constraint for IOBIOB_usage_post1.PNGXDC constraints for IOB

=== Highly appreciated if any help or suggestion.

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Registered: ‎01-22-2015

Re: IOB component usage in Synthesis and XDC file ?


The language template you identified helps you write the following XDC constraint:

     set_property LOC IOB_X<#>Y<#> [get_cells <cell>]

You can use this constraint to physically place a cell (typically a register) into an IO Block (IOB). There is an IOB located very near each of the IO ports/pins of the FPGA.  Also, this constraint allows you to identify a specific IOB using the physical location address, X<#>Y<#>.  

Using a specific address (ie. X<#>Y<#>) when placing a register into the IOB is usually not the preferred method.   It is often better to use the following XDC constraint:     

     set_property IOB true [get_cells <register cells>]

This constraint tells Vivado that you want the cell (typically a register) placed into an IOB, but does not say which IOB.  Vivado will then use the IOB closest to the FPGA port/pin that is connected to the register, which is usually what you want.

When a register is connected to a port/pin of the FPGA, it is also possible to place the register into the IOB with the following XDC constraint that refers to the port rather than the register.

     set_property IOB true [get_ports <port>]

We usually place registers into the IOB when the register is part of an FPGA IO interface (eg. FPGA reads data from an external ADC). This register placement is necessary to maintain consistent path lengths for the interface from implementation to implementation.


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