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Visitor to_skishor
Visitor
2,826 Views
Registered: ‎01-20-2009

IP core and simulation

Hi,

 I m using ISE 10.1.3 and ModelSimXE 6.3c.

I'm using Single port RAM IP core which has got 1 clk latency. However I don't want any latency.

In such case what can be done?

 

The same RAM I've coded on my own. However how do I initialize it on reset and which construct I should use so that post and routing can be done?

 

Pl. relpy.

 

Kishor 

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