I am evaluating ISE WebPack 11 (released a few days ago).
I created a new project with only one IP core (I tried a 1Kx32 single port BRAM-based RAM and a 32 bits multiply-adder) instanciated from a schematic set as the top module (since an IP core cannot be a top module). In XST report, 0 LUT, 0 FF and 0 BRAM are used ! But MAP and PAR are OK (LUT, FF and BRAM usage are coherent with those obtained with ISE 10.1 and the design is successfuly implemented).
So all is as if cores were not read during synthesis in ISE 11. Of course, the option "Read cores" is checked (default). And of course, the LUT, FF and BRAM usage are OK (for example 1 BRAM used for the 1Kx32 RAM) in the synthesis report in ISE 10.1.
Can you reproduce this case ?
Have you got a solution to get a correct device resource estimation of the synthesized design ?