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Visitor 463717263
Visitor
4,114 Views
Registered: ‎12-16-2013

always @ (posedge clk or negedge rst)
begin
if (!rst)
sram_sel<=0;
else
din_en_reg<=sram_din_en;
end

always @ (posedge clk or negedge rst )
begin
if(sram_din_en)
begin
if(addr1_reg==8'd63) 
begin
addr1_reg<=32'h0;
sram_sel<=~sram_sel; 
end
else
addr1_reg<=addr1_reg+1;
end
else
addr1_reg<=32'h0;
end

always @ (posedge clk or negedge rst)
begin
if(sram_din_en)
begin
if(addr2_reg==8'd63)
begin
addr2_reg<=32'h0;
end
else
addr2_reg<=addr2_reg+1;
end
else
addr2_reg<=32'h0;
end

 

error The logic for < addr1_reg > does not match a known FF or Latch The template .can you tell me how to solve this problem?

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1 Solution

Accepted Solutions
Historian
Historian
5,304 Views
Registered: ‎01-23-2009

Re: ISE RTL

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Your sensitivity list is "always @(posedge clk or negedge rst)" this means that the block will be evaluated on the rising edge of the clock or the falling edge of rst. However, you don't have an if (!rst) clause in the block itself, which completes the definition of a flip-flop with active low asynchronous reset. Without this, the tool sees this as flip-flops with two different clocks, which doesn't exist.

 

Avrum

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4 Replies
Historian
Historian
5,305 Views
Registered: ‎01-23-2009

Re: ISE RTL

Jump to solution

Your sensitivity list is "always @(posedge clk or negedge rst)" this means that the block will be evaluated on the rising edge of the clock or the falling edge of rst. However, you don't have an if (!rst) clause in the block itself, which completes the definition of a flip-flop with active low asynchronous reset. Without this, the tool sees this as flip-flops with two different clocks, which doesn't exist.

 

Avrum

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Visitor 463717263
Visitor
4,101 Views
Registered: ‎12-16-2013

Re: ISE RTL

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thanks,Avrum.
what i want to do is a ping-pang RAM structure.when read SRAM1,write SRAM2.when read SRAM2,write SRAM1.what should i do to realise it?

floyd
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Visitor 463717263
Visitor
4,097 Views
Registered: ‎12-16-2013

Re: ISE RTL

Jump to solution
module sram_ctr(clk,
rst,
data1,
addr1,
ce1,
we1,
oe1,
data2,
addr2,
ce2,
we2,
oe2,
sram_din,
sram_din_en,
sram_dout,
sram_dout_en);
//port
input clk,rst,sram_din_en,sram_dout_en;
input [31:0] sram_din;
output [31:0] sram_dout;
inout [31:0] data1,data2;
output [31:0] addr1,addr2;
output ce1,we1,oe1,ce2,we2,oe2;
//intra port
reg [31 :0] sram_dout;
reg [31:0] addr1_reg,addr2_reg;
wire [31:0] addr1,addr2;
wire [31 :0] data1,data2;
wire ce1,we1,oe1,ce2,we2,oe2;
reg sram_sel;
wire [31:0] data_reg;
reg din_en_reg;//延时din_en_reg
//复位
always @ (posedge clk or negedge rst)
begin
if (!rst)
sram_sel<=0;
else
din_en_reg<=sram_din_en;
end
//设置写ram地址
always @ (posedge clk )
begin
if(sram_din_en)
begin
if(addr1_reg==8'd63) //限定每次传输额度
begin
addr1_reg<=32'h0;
sram_sel_flag<=~sram_sel; //切换读写标志,达到限定传输额度就交换
end
else
addr1_reg<=addr1_reg+1;
end
else
addr1_reg<=32'h0;
end
//设置读ram地址
always @ (posedge clk )
begin
if(sram_din_en)
begin
if(addr2_reg==8'd63)
begin
addr2_reg<=32'h0;
end
else
addr2_reg<=addr2_reg+1;
end
else
addr2_reg<=32'h0;
end
//乒乓读写ram逻辑
assign ce1=1'b0;
assign ce2=1'b0;
assign we1=(!sram_sel&&sram_din_en)?(~clk):(!sram_din_en)?1'b0:1'b1;
assign oe1=( sram_sel&&sram_din_en)?clk:1'b1;
assign we2=( sram_sel&&sram_din_en)?(~clk):(!sram_din_en)?1'b0:1'b1;
assign oe2=(!sram_sel&&sram_din_en)?clk:1'b1;
assign addr1=(!sram_sel&&sram_din_en)?addr1_reg:addr2_reg;
assign addr2=(!sram_sel&&sram_din_en)?addr2_reg:addr1_reg;
assign data1=(!sram_sel&&sram_din_en)?sram_din:8'hzz;
assign data2=( sram_sel&&sram_din_en)?sram_din:8'hzz;
assign data_reg=(!sram_sel&&sram_din_en)?data2:( sram_sel&&sram_din_en)?data1:sram_din;
always @ (posedge clk )
begin
if (sram_dout_en)
begin
sram_dout<=data_reg;
end
end
endmodule
here is my code ! where is the problem!
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Historian
Historian
4,058 Views
Registered: ‎02-25-2008

Re: ISE RTL

Jump to solution

@463717263 wrote:
here is my code ! where is the problem!

It's not formatted, and as such is impossible for a human to read.

----------------------------Yes, I do this for a living.
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