09-12-2019 08:37 AM
I have a problem with finite state machine using ise webpack 14.7 .
I have fine working devices that are my Rx and Tx box .
I have merged Tx and Rx vhdl code and the result instead a state machine of 39 states is a rom 39X1 .
If I stop the route of code to reset the sysntetizer recognize it like a 39 states machine BUT WARN me that it don't reach the others 38 states.
09-12-2019 09:01 AM
I'll try to explain better.
I have two piece of vhdl code that describes two finite states machines (Rx and Tx) that works fine.
If I try to merge in a one vhdl code with one state machine, doubled size respect ones, I get the problem that don't recognize like a fsm but like a rom.
The merging is done by appropriate change and i don't get any error or extra warning.
Is there same limit for states machine?
09-12-2019 09:07 AM
Please post your code as an attatchment,
there is no practical limit to state mahchine sizes outside the size of the chip.
This sounds very much like a codding feature,
Post the code and we can try help.
Post the failing and passing code, along with the test bench you have please.
09-13-2019 01:31 AM