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bfung
Explorer
Explorer
1,827 Views
Registered: ‎03-27-2017

Identifying Logic Loop

Hello, I require assistance to interpret the synthesis report to resolve timing loops. From the report:

 

Found timing loop:
0: RXStreamChannel__GCM0:/i_4/i_268/O (GATE_2_11)
1: RXStreamChannel__GCM0:/i_4/i_268/I0 (GATE_2_11)
2: RXStreamChannel__GCM0:/i_4/i_267/O (GATE_2_14_OR)
3: RXStreamChannel__GCM0:/i_4/i_267/I0 (GATE_2_14_OR)
4: RXStreamChannel__GCM0:/i_4/i_266/O (GATE_2_14_OR)
5: RXStreamChannel__GCM0:/i_4/i_266/I0 (GATE_2_14_OR)
6: RXStreamChannel__GCM0:/i_4/i_530/O (GATE_2_14_OR)
7: RXStreamChannel__GCM0:/i_4/i_530/I0 (GATE_2_14_OR)
8: RXStreamChannel__GCM0:/i_4/i_393/O (GATE_2_14_OR)
9: RXStreamChannel__GCM0:/i_4/i_393/I0 (GATE_2_14_OR)
10: RXStreamChannel__GCM0:/i_4/i_392/O (GATE_2_14_OR)
11: RXStreamChannel__GCM0:/i_4/i_392/I0 (GATE_2_14_OR)
12: RXStreamChannel__GCM0:/i_4/i_391/O (GATE_2_2)
13: RXStreamChannel__GCM0:/i_4/i_391/I0 (GATE_2_2)
14: RXStreamChannel__GCM0:/i_4/i_268/O (GATE_2_11)

 

This seems like a hierarchy to me, where RXStreamChannel is one of my modules and then the following becomes more specific in the net/gate that is in the path of the timing loop? How can I identify these elements in the schematic/net-list? An explanation of the hierarchy and what's its describing would be great. Thanks!

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iobass
Visitor
Visitor
1,762 Views
Registered: ‎08-18-2017

This error is new to me, but a loop usually indicates something feeding back on itself. Can you examine the logic of your RXStreamChannel component to see if there is a combinational loop (no flip-flop)?
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