I have two EDIF netlists (no .xci files) for two pieces of IP (3'rd party vendor supplied) .
I need to "implement" a design which connects 3 instantiations of one netlist with 1 instantiations of the other.
The top level modules of each of netlists can be connected. I have written a verilog "wrapper file" which "connects"
3 instantiations of 1 IP component with 1 instantiations of the other.
So is it better to write the "wrapper" file as an EDIF netlist and read the wrapper EDIF and the IP instances into the
imlementation project as EDIF netlists and run "link design".
Write verilog for each EDIF netlists and create a proven with 3 verilog netlists for implementation.
Is there no preference.
For EDIF file you will need a stub: https://www.xilinx.com/support/answers/54074.html
You can also use this flow: create a post-synthesis project --> Add netlist files --> Open Synthesized Design -> use write_verilog to generate master netlist.
I would recommend to go with EDIF-stub flow as you already have a wrapper for your design.