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Visitor am17an
Visitor
616 Views
Registered: ‎03-12-2018

Implementing a big synthesisable ram

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Hi I'm using XCKU035, which has 36kb, 18kb primitives for BRAMs. I'm trying to implement an array of size 400kb. What is the best way to achieve this? If I just specify the 400kb size, the synthesis tools chokes. The other choices I see are implementing 18kb rams in a 2d array and using those. 

 

Please help. 

 

Thanks

 

 

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Scholar u4223374
Scholar
824 Views
Registered: ‎04-26-2015

Re: Implementing a big synthesisable ram

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That's odd, the synthesis tool should have no trouble handling 400Kb (or 400KB, for that matter). I've used RAMs that big before.

 

My guess would be that you've got an access pattern that isn't compatible with block RAM - trying to set the address and get the data in one cycle (BRAM requires a clock edge), trying to read/write more than two elements per cycle, etc. In that case the synthesis tool will go back to implementing it as registers, and a mux to access >100K registers will definitely cause it to choke.

2 Replies
Scholar u4223374
Scholar
825 Views
Registered: ‎04-26-2015

Re: Implementing a big synthesisable ram

Jump to solution

That's odd, the synthesis tool should have no trouble handling 400Kb (or 400KB, for that matter). I've used RAMs that big before.

 

My guess would be that you've got an access pattern that isn't compatible with block RAM - trying to set the address and get the data in one cycle (BRAM requires a clock edge), trying to read/write more than two elements per cycle, etc. In that case the synthesis tool will go back to implementing it as registers, and a mux to access >100K registers will definitely cause it to choke.

Visitor am17an
Visitor
552 Views
Registered: ‎03-12-2018

Re: Implementing a big synthesisable ram

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Yup, that was the problem. 

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