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Adventurer
Adventurer
8,569 Views
Registered: ‎04-25-2014

Infered block ram warning [Synth 8-3514]

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Getting the following error

[Synth 8-3514] cannot infer block ram on a non-memory variable 'RAM'

 

In my code

type ram_type is array (63 downto 0) of std_logic_vector(31 downto 0);

signal RAM : ram_type;

attribute ram_style : string;

attribute ram_style of RAM : signal is "block";  -- <-- Line where synth 8-3514 points to

 

Thanks for the help

Wesley

 

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Adventurer
Adventurer
16,306 Views
Registered: ‎04-25-2014

Re: Infered block ram warning [Synth 8-3514]

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There is no reset for the RAM(0), RAM(1) signals.

They are concurrently assigned constants
RAM(63) <= x"C67178f2";

Therefore I believe my problem is the synth tool sees these as constants & not necessary ram.
After removing the block attribute I have removed this warning
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4 Replies
Moderator
Moderator
8,554 Views
Registered: ‎07-21-2014

Re: Infered block ram warning [Synth 8-3514]

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@wesleytaylor

 

We may not be able to comment by only looking at the memory declaration, can you share the small testcase/RTL file here?

What type of reset you are using?

 

Thanks,
Anusheel
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Adventurer
Adventurer
16,307 Views
Registered: ‎04-25-2014

Re: Infered block ram warning [Synth 8-3514]

Jump to solution
There is no reset for the RAM(0), RAM(1) signals.

They are concurrently assigned constants
RAM(63) <= x"C67178f2";

Therefore I believe my problem is the synth tool sees these as constants & not necessary ram.
After removing the block attribute I have removed this warning
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Moderator
Moderator
8,540 Views
Registered: ‎01-16-2013

Re: Infered block ram warning [Synth 8-3514]

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@wesleytaylor,

 

Glad to know that you have resolved the issue. You can check page number 99-100 in below Synthesis user guide for various RAM coding guidelines and Techiques:

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_4/ug901-vivado-synthesis.pdf

 

As the issue is resolved, Kindly close this thread by marking the post as "Accept as solution".

 

--Syed

 

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Did you check our new quick reference timing closure guide (UG1292)?
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Moderator
Moderator
8,527 Views
Registered: ‎07-21-2014

Re: Infered block ram warning [Synth 8-3514]

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@wesleytaylor

 

Yes, I guess you are correct. Removing attribute will clear your log, but if you want infer a BRAM for this memory logic you may need to change the RTL description.

Share your memory file here if you need any help in memory RTL.

 

Thanks,
Anusheel
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