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verylsi
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Registered: ‎10-04-2016

Infering block ram for LUT

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I want to synthesize LUT into block memory to save area .

The LUT, is purely combinatorial. is there anyway by which I can force the tool to infer LUT as rom in block memory ?

 

I tried with rom_type attribute in rtl as shown in attached image, but it did not infer any block memory tile.

 

Thanks in advance

rom_type.PNG
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avrumw
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Registered: ‎01-23-2009

The block RAMs in all Xilinx families are "Synchronous Read" RAMs, meaning they have one clock cycle of latency on the read. To read from the RAM, the address must be stable prior to the rising edge of clock, and the data will then be available after the rising edge of the clock. This is shown in the Memory Resources User Guide for the technology you are using (you haven't even told us what family you are using) - so for example, for Virtex 6, this is shown in UG363 (v1.8) in several places, but maybe most clearly in figure 1-15.

 

Since the block "ROM" is implemented in the block RAM resource, it has to have the same characteristics.

 

One trick that can work at low frequencies, though, is to clock the RAM/ROM on the falling edge of the clock. This can make the RAM look like it is combinatorial...

 

   - on the rising edge of the clock, the flip-flops that generate address update

      - there can be some amount of combinatorial logic between the FFs that generate the address and the address pins of the RAM

   - on the falling edge of the clock, the RAM is clocked

      - as long as the combinatorial delay and routing is less than 1/2 clock period, this will satisfy the setup requirement of the RAM

   - on the next rising edge the flip-flops that capture the results of the RAM update

      - there can be combinatorial logic on the path between the Q outputs of the RAM and the capture flip-flops

 

When viewed as a whole, the path from the FFs that generate the address to the FFs that capture the resulting data only take one clock period (thus the RAM/ROM looks like it is combinatorial).

 

But, this only works at low frequencies - the Clock-to-out of the RAMs is pretty large - you might get this to work at 100MHz or even a bit faster, but it is not likely at 200MHz or higher.

 

Avrum

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balkris
Xilinx Employee
Xilinx Employee
6,745 Views
Registered: ‎08-01-2008
use attributes . You may try with synthesis property

check this guide

https://www.xilinx.com/itp/xilinx10/books/docs/xst/xst.pdf

Check language templates as well
Thanks and Regards
Balkrishan
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anusheel
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Registered: ‎07-21-2014

@verylsi

 

Try to modify your code in such a way that it behaves like a ROM. Initialize memory location with the desired INIT value and then based on address read the location from memory.

 

Refer UG901 to check ROM coding styles.

 

Thanks,
Anusheel
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u4223374
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Registered: ‎04-26-2015

I don't think you can do "purely combinatorial" with block RAM. It's reads data on the clock edge; you have to give it a clock cycle between setting the address and getting the data.

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verylsi
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Registered: ‎10-04-2016
I also have doubts over inferring block ram of purely combinatorial logic. where can i confirm ?
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avrumw
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10,984 Views
Registered: ‎01-23-2009

The block RAMs in all Xilinx families are "Synchronous Read" RAMs, meaning they have one clock cycle of latency on the read. To read from the RAM, the address must be stable prior to the rising edge of clock, and the data will then be available after the rising edge of the clock. This is shown in the Memory Resources User Guide for the technology you are using (you haven't even told us what family you are using) - so for example, for Virtex 6, this is shown in UG363 (v1.8) in several places, but maybe most clearly in figure 1-15.

 

Since the block "ROM" is implemented in the block RAM resource, it has to have the same characteristics.

 

One trick that can work at low frequencies, though, is to clock the RAM/ROM on the falling edge of the clock. This can make the RAM look like it is combinatorial...

 

   - on the rising edge of the clock, the flip-flops that generate address update

      - there can be some amount of combinatorial logic between the FFs that generate the address and the address pins of the RAM

   - on the falling edge of the clock, the RAM is clocked

      - as long as the combinatorial delay and routing is less than 1/2 clock period, this will satisfy the setup requirement of the RAM

   - on the next rising edge the flip-flops that capture the results of the RAM update

      - there can be combinatorial logic on the path between the Q outputs of the RAM and the capture flip-flops

 

When viewed as a whole, the path from the FFs that generate the address to the FFs that capture the resulting data only take one clock period (thus the RAM/ROM looks like it is combinatorial).

 

But, this only works at low frequencies - the Clock-to-out of the RAMs is pretty large - you might get this to work at 100MHz or even a bit faster, but it is not likely at 200MHz or higher.

 

Avrum

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anusheel
Moderator
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Registered: ‎07-21-2014

@verylsi

 

If the logic does not have a clock coming in the design then tool will not infer any ROM, as BRAM/memory needs a clock, the very first thing tool will look in the RTL to infer ROM is clock. There is no way to infer ROM for purely combination logic, you can use the suggestion mentioned by Avrum if your design allows.

 

Thanks,
Anusheel
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DiamondBound
Observer
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Registered: ‎03-18-2020

Note: You must specify all values, meaning you cannot use the 'default' construct in the case statement.  

--Ross

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