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ogacns94

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03-22-2019 02:50 AM - edited 03-22-2019 04:13 AM

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Registered:
03-22-2019

Infering one DSP48E for multiply and add opperation (round multiply) in ISE 14.7

Hello everyone!

I am constrained to using ISE 14.7 because I am using an old board that has a Spartan-3A and Virtex 5 FPGA. I am targeting Virtex 5.

I want to implement multplication with rounding of two fixed point numbers in VHDL that is mapped directly to **one** DSP48E block. By looking at the datasheet (https://www.xilinx.com/support/documentation/user_guides/ug193.pdf, page 14), this seems possible. I plan to do it by multiplying and then adding with a vector that has 1 in the possition needed for rounding:

A = 001011.11

B = 0110.1001

A*B = xxxxxxxxxx.xxxxxx

one = 0000000000.000100

A*B+one;

C = xxx.xxx

This is my VHDL code:

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity unsigned_round_multiplier is generic( IN0_INT_BITS : integer:= 4; IN0_FRAC_BITS : integer:= 14; IN1_INT_BITS : integer:= 0; IN1_FRAC_BITS : integer:= 25; OUT_INT_BITS : integer:= 0; OUT_FRAC_BITS : integer:= 25 ); port( in0_i : in std_logic_vector ((IN0_INT_BITS+IN0_FRAC_BITS)-1 downto 0); in1_i : in std_logic_vector ((IN1_INT_BITS+IN1_FRAC_BITS)-1 downto 0); out_o : out std_logic_vector ((OUT_INT_BITS+OUT_FRAC_BITS)-1 downto 0); ); end unsigned_round_multiplier; architecture rtl of unsigned_round_multiplier is signal mult : unsigned((IN0_INT_BITS+IN1_INT_BITS+IN0_FRAC_BITS+IN1_FRAC_BITS)-1 downto 0); signal round : unsigned((OUT_INT_BITS+OUT_FRAC_BITS) downto 0); signal one_final_i : unsigned((IN0_INT_BITS+IN1_INT_BITS+IN0_FRAC_BITS+IN1_FRAC_BITS)-1 downto 0); constant one : std_logic_vector((IN0_INT_BITS+IN1_INT_BITS+OUT_FRAC_BITS) downto 0) := (0 => '1', others => '0'); constant one_padding : std_logic_vector((IN0_FRAC_BITS+IN1_FRAC_BITS-1-OUT_FRAC_BITS-1) downto 0) := (others => '0'); attribute use_dsp48 : string; attribute use_dsp48 of mult : signal is "yes"; begin mult <= unsigned(in0_i)*unsigned(in1_i) + unsigned(one&one_padding); out_o <= std_logic_vector(mult((OUT_INT_BITS+IN0_FRAC_BITS+IN1_FRAC_BITS-1) downto (IN0_FRAC_BITS+IN1_FRAC_BITS-OUT_FRAC_BITS))); end architecture rtl;

ISE just won't map it to **one** DSP. Whatever I do, it is either mapped to two DSPs or to one DSP and a sequence of adders used from the slices. I tried adding a clock signal, separating it in two expressions, etc. It never maps it to one DSP only.

Does anybody have experience with this?

Thanks in advance!

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