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Explorer
Explorer
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Registered: ‎04-20-2010

Inferred BRAM organization information?

Env: Spartan-6 (LX9 / LX16), ISE 14.7, Win7

I'm trying to use data2mem to update the inferred memory in my design (to update ROM code and data without having to run systhesis / map / place-and-route over and over).

I learned the hard way that the MEM files used with data2mem must have the data values in a format that exactly matches the organization of the BRAMs in the design.  I was originally under the impression that data2mem would do the translation and slice the data to match the BRAM organization (hard lesson learned for sure).

I prefer to infer memory whenever possible, so when I create something like an 8Kx8, 16Kx8, or 32Kx8 memory, how can I see what kind of organization the synthesizer came up with?

For example, it seems that an inferred 8Kx8 memory will use four BRAMs in an 8Kx2-bit organization, with each BRAM contributing 2-bits to each byte.  This means the values in the MEM file have to be bit-sliced on 2-bit boundaries as well.  And I have no idea how a 16Kx8 or 32Kx8 would be organized.

Any information on how to find the final organization of inferred memory would be greatly appreciated.

Matthew

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-30-2019

Hi @matthew180 ,

I have not tried this in ISE14.7.

But in vivado, there is a TCL command updatemem which is used to populate the RAM's in your design with whatever content you want.

This command takes mem file, bit file and mmi file as input and outputs a new bit file

In this, the desired contents to be populated in RAM's (which you have mentioned in mem file) are merged with the bit file and a new bit file is created with updated contents of RAM.

Now the question how does vivado know - In what RAM what data to put so that altogether these combinations of BRAM will act like common memory made up of independent RAM's.

This information (how RAM's are configured to act as a single memory) is present in the mmi file. 

So not sure about ISE but in vivado, this is how you see the memory configuration (mmi file).

I will try the same with data2mem in ISE and let you know. 

meanwhile, other users who have tried this might give you some insight

--Suraj 

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Explorer
Explorer
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Registered: ‎04-20-2010

Hello Suraj,

I do not see any mmi files in the ISE project.  I have created a bmm file (loader.bmm) with an initial layout, and the place-and-route process creates an updated version of that file (loader_bd.bmm) with the location information filled in.  It looks something like this:

ADDRESS_SPACE loader RAMB16 [0x00000000:0x00003FFF]
	BUS_BLOCK
		phoenix/loader/Mram_ram_q1 RAMB16 [7:0] [0:2047] PLACED = X0Y30;
	END_BUS_BLOCK;

	BUS_BLOCK
		phoenix/loader/Mram_ram_q2 RAMB16 [7:0] [2048:4095] PLACED = X0Y26;
	END_BUS_BLOCK;

	BUS_BLOCK
		phoenix/loader/Mram_ram_q3 RAMB16 [7:0] [4096:6143] PLACED = X1Y14;
	END_BUS_BLOCK;

	BUS_BLOCK
		phoenix/loader/Mram_ram_q4 RAMB16 [7:0] [6144:8191] PLACED = X1Y12;
	END_BUS_BLOCK;

	BUS_BLOCK
		phoenix/loader/Mram_ram_q5 RAMB16 [7:0] [8192:10239] PLACED = X1Y28;
	END_BUS_BLOCK;

	BUS_BLOCK
		phoenix/loader/Mram_ram_q6 RAMB16 [7:0] [10240:12287] PLACED = X1Y30;
	END_BUS_BLOCK;

	BUS_BLOCK
		phoenix/loader/Mram_ram_q7 RAMB16 [7:0] [12288:14335] PLACED = X1Y16;
	END_BUS_BLOCK;

	BUS_BLOCK
		phoenix/loader/Mram_ram_q8 RAMB16 [7:0] [14336:16383] PLACED = X1Y10;
	END_BUS_BLOCK;
END_ADDRESS_SPACE;

The tool added the addres range information ([0:2047], etc.) and the "PLACED" information.  The problem is, the data-range information ([7:0]) is wrong compared to how the memory was actaully organized.  The reality is that eight BRAMs were used in a 16Kx1-bit configuration, so I would expect each block to say:

[0:0] [0:16383]

[1:1] [0:16383]

...

[7:7] [0:16383]

This would let me know that the mem file I have to generate from my code-binary needs to be bit-sliced (which is highly inconvenient, but at least knowing the organization makes it easier.)

The other confusing part is, the "input" bmm file I have to provide to the tool has to specify the data range information, so I provide [7:0] for each block because that is what I would *like*.  But the output *_bd.bmm file is not being updated with the data-ranges as they were actually generated.

Also, once the memory grows over 16Kx8-bit, I do not know how the inferred memory will be laided out since a BRAM is maxed out at 16Kx1 (not couting parity in this case).  For example, how would a 32Kx8-bit memory be oragnized?

Matthew

 

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Scholar
Scholar
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Registered: ‎04-26-2012

@matthew180   "I'm trying to use data2mem to update the inferred memory in my design"

There is notionally a flow for DATA2MEM that finds BRAMs by name and generates the BMM, but:

  • it's not well documented
  • can fail silently
  • hard-codes the absolute pathname of the BMM file into the NCD file in some versions of ISE

The following Perl script (from the 2006-vintage openfire project) examines an NCD using the ISE XDL tool, finds BRAMs by searching for the processor name (for a known memory organization), and generates the corresponding BMM file:

   https://github.com/xialixun/OpenIce/blob/master/utils/openfire_bram.pl

Here's some old newsgroup discussions of finding BRAM locations for data2mem by various methods:

  https://groups.google.com/d/msg/comp.arch.fpga/TrlngKEff9w/mncdZAfsCxcJ

  https://groups.google.com/d/msg/comp.arch.fpga/2AmXIEK9i2E/3EHwlHc176AJ

-Brian

 

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Xilinx Employee
Xilinx Employee
350 Views
Registered: ‎01-30-2019

@matthew180 

I had the same issue what you are describing and it was a tool bug which was found in Vivado 2018.x and fixed in Vivado 2019.1

Since ISE is in maintenance mode there is no development and the last version of ISE design Suite is 14.7, so you have to manually write the bmm file

please follow this link and let us know

https://www.xilinx.com/Attachment/Xilinx_Answer_46945_Data2Mem_Usage_and_Debugging_Guide.pdf

--Suraj 

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