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rtfinch
Adventurer
Adventurer
1,134 Views
Registered: ‎01-06-2016

Initial begin not initializing in synthesis

I have run into the following where an initial begin did not set the value of a register in synthesis when a slice of the register was used (it set the whole register to zero). This is under Vivado 18.2, windows 10 pro. As a fix it was easy to just set the whole register in this case.
 
initial begin
 for (n = 0; n < 256; n = n + 1) begin
  sprite_color[n] <= {6'h00,8'h00,n[7:5],5'd0,n[4:3],6'd0,n[2:0],5'd0};
//  sprite_color[n][31:0] <= {8'h00,n[7:5],5'd0,n[4:3],6'd0,n[2:0],5'd0}; // <- doesn't work
 end
 for (n = 0; n < 32; n = n + 1) begin
  sprite_ph[n] <= 220 + n * 40;
  sprite_pv[n] <= 41 + n * 20;
  sprite_pz[n] <= 8'h00;
  spriteMcnt[n] <= 80 * 32;
  spriteBmp[n] <= 64'hFFFFFFFFFFFFFFFF;
  spriteAddr[n] <= 32'h40000 + (n << 12);
 end
end
 
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4 Replies
hemangd
Moderator
Moderator
1,110 Views
Registered: ‎03-16-2017

Hi @rtfinch,

Can you share the full source code of this testcase to evaluate it at our end?

 

Regards,

hemangd

Regards,
hemangd

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rtfinch
Adventurer
Adventurer
1,103 Views
Registered: ‎01-06-2016

I've attached the file. I tested the output in an FPGA and checked visually switching between the two lines. The project itself has about 150 files in it. Some of them are under different directories. I can try and zip up all the files but I might miss something or include more than what's needed.

 

 

 

 

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rshekhaw
Xilinx Employee
Xilinx Employee
1,052 Views
Registered: ‎05-22-2018

Hi @rtfinch,

 

I check the test case share from your end and at my end there is no difference during initialization of the array considering both statements(checked in simulation):

 sprite_color[n] <= {6'h00,8'h00,n[7:5],5'd0,n[4:3],6'd0,n[2:0],5'd0};
 sprite_color[n][31:0] <= {8'h00,n[7:5],5'd0,n[4:3],6'd0,n[2:0],5'd0}; // <- doesn't work

 

Can you please elaborate the issue and your requirement more precisely.

 

thanks,

Raj Singh.

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rtfinch
Adventurer
Adventurer
1,029 Views
Registered: ‎01-06-2016

I'm not sure but I think it may work in simulation but not when synthesized. It doesn't work when a bitfile is loaded into the FPGA.

I just noticed a warning during synthesis that may have something to do with this. Unfortunately I didn't capture the message. It said something about a register not being initialized to the expected value. It's just a thing that caught me off guard because I expected it to work. But there's an easy work-around, just initialize all the bits. I had done this in a couple of places. One place was a 280 bit vector where only a couple of the bits needed to be initialized.

 

 

 

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