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Voyager
Voyager
685 Views
Registered: ‎08-16-2018

Initialize memory from file in VHDL

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I have a relatively large chunk of constants hardcoded in a VHDL module. Functionally no problem.

I just feel is not a good style... so, is there a way of putting that data in a separate file that is somehow read, or attached to, whatever is called, into the memory?

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-14-2008

You can use File IO in VHDL.

There is an example in UG901.

Search for "Specifying RAM Initial Contents in an External Data File" in UG901.

-vivian

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Xilinx Employee
Xilinx Employee
674 Views
Registered: ‎05-14-2008

You can use File IO in VHDL.

There is an example in UG901.

Search for "Specifying RAM Initial Contents in an External Data File" in UG901.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
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667 Views
Registered: ‎01-22-2015

I feel that constants with descriptive names are an important part of documenting my VHDL. So, I like to define them near where they are used.

I suppose you could place constants into block memory and use a COE file to initialize the memory with the constants.  -but then the constants are kinda nameless and invisible.

If you think your constants are cluttering your tidy VHDL component file, how about shoving them into the VHDL package file for your project?

Mark