Initialize memory from file in VHDL

[johnvivm]

I have a relatively large chunk of constants hardcoded in a VHDL module. Functionally no problem.

I just feel is not a good style... so, is there a way of putting that data in a separate file that is somehow read, or attached to, whatever is called, into the memory?

[viviany · Accepted solution]

You can use File IO in VHDL.

There is an example in UG901.

Search for "Specifying RAM Initial Contents in an External Data File" in UG901.

-vivian

[markg@prosensing.com]

I feel that constants with descriptive names are an important part of documenting my VHDL. So, I like to define them near where they are used.

I suppose you could place constants into block memory and use a COE file to initialize the memory with the constants.  -but then the constants are kinda nameless and invisible.

If you think your constants are cluttering your tidy VHDL component file, how about shoving them into the VHDL package file for your project?

Mark