Initializing an array from text file for synthesis

[Charlycop]

Hi, I want to initialise a large array in my IP. I'm using this package to get the values from a txt file, and it works great in simulation but fail during synthesis.

Here are the errors :

• [Synth 8-5765] size mismatch in assignment; read failed ["C:/FPGA2/ChaHuSi_IP_accel/ChaHuSi_IP_accel.srcs/sources_1/new/tableaupoids.vhd":21]
• [Synth 8-421] mismatched array sizes in rhs and lhs of assignment ["C:/FPGA2/ChaHuSi_IP_accel/ChaHuSi_IP_accel.srcs/sources_1/new/tableaupoids.vhd":3]

package pkg is
  type output_t is array(0 to 14) of integer;  -- Just change size
  constant output : output_t;  -- Value assign is deferred
end package;

library std;
use std.textio.all;

package body pkg is

  -- Entries in output without value in file are assigned to 0
  impure function output_init return output_t is
    file vec_file: text open read_mode is "mytext.mem";
    variable iline: line;
    variable data_read: integer;
    variable x: integer := 0;
    variable res_t : output_t := (others => 0);
  begin
    while not endfile (vec_file) loop
      readline (vec_file, iline);
      read(iline,data_read);
      res_t(x) := data_read;
      x := x + 1;
    end loop;
    return res_t;
  end function;

  constant output : output_t := output_init;

end package body;

Is it synthetisable ? if yes, what is wrong ? I mean, why is it working in simulation and not in synthesis ?

Thanks.

[drjohnsmith · Accepted solution]

No  need to invent your own

   many pre existing ways on the web

https://vhdlwhiz.com/initialize-ram-from-file/

[brimdavis]

@Charlycop   "why is it working in simulation and not in synthesis ?"

The last time I checked (a couple years ago), Vivado Synthesis still had very poor file I/O support as compared with XST - I've seen similar file parsing code, that worked in XST, fail in Vivado Synthesis.

I typically use a constant array in a package for initialization as a workaround; the package file can be auto-generated fairy easily in MATLAB/Perl/etc. to fit into whatever flow normally generates the data file that you wish to parse.

Some notes/documentation links/parser examples on this 2017 thread:

    https://forums.xilinx.com/t5/Synthesis/File-Integer-read-size-mismatch-in-assignment-read-failed/m-p/781364/highlight/true#M22250 

The latest 2020.2 UG901 Synthesis manual  still states that file I/O is limited to a one-entry-per-line text file in binary or hex format, see chapter 4 section "Initializing RAM Contents => Specifying RAM Initial Contents in an External Data File"

You might be able to get your code to work in Vivado with some changes to data types (std_logic_vector) and your file format so as to read in hex | binary strings from your file.

( I haven't checked recently to see if they've added better file I/O support to Vivado synthesis without updating the documentation )

-Brian

[Charlycop]

I did it using a text file with one hexadecimal value per line, thanks !