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Visitor elrhod
Visitor
172 Views
Registered: ‎03-01-2019

Input connected to const zero after synthsis

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Hello, thank you for your help in this issue!

I have an input (named "left") that is connected to zero after synthesis. 

When I run RTL synthesis the same input is connected as expected (as presented below). Hog_00_after_RTL_synth.PNGAfter RTL Synthesis.

After running synthesis the same input (left) is tight to zero (as presented below).

Hog_00_after_synth.PNGAfter Synthesis

The same input is also connected in another block and synthesis did not connect it to zero.

Also, the logic inside the HogGen block uses this input and therefore there is no logic reason to connect it to zero.

In attach follows the synthesis log. Apparently there is no warning related to this port that explains why synthesis is connecting it to zero.

Am I missing something or is it a synthesis bug?

Thank you for your help.

Regards.

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1 Solution

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Xilinx Employee
Xilinx Employee
103 Views
Registered: ‎05-14-2008

Re: Input connected to const zero after synthsis

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Have you verified if the post-synthesis netlist functions well by simulation?

This might be due to some cross-boundary optimization as two pins connected/share the same net.

You can try to set -flatten_hierarchy to none, or add "keep_hierarchy" attribute to HogGen module in RTL, and see if this gives different result.

Anyway if the post-synthesis simulation shows good function, this is not an issue.

-vivian

6 Replies
Xilinx Employee
Xilinx Employee
149 Views
Registered: ‎05-14-2008

Re: Input connected to const zero after synthsis

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Can you try applying "dont_touch" constraint to the nets that are connected to the left pin in the Elaborated design?

set_property DONT_TOUCH true [get_nets <net_name found in the Elaborated design>]

Put this constraint in the XDC and run Synthesis.

Does it help?

-vivian

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Visitor elrhod
Visitor
121 Views
Registered: ‎03-01-2019

Re: Input connected to const zero after synthsis

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Hi Vivian. Thank you for your reply!

Sorry but it did not work. Even after I run the the "DONT_TOUCH" property set I got the same connection to const ZERO problem.

set_property DONT_TOUCH true [get_nets -of_objects [get_pins -of_objects [get_cells Hog_block1/Hog_calc_0_0] -filter {NAME =~*left*}]]

Analysing the code looking for some pathern I found that the connection to ZERO happens whenever an input is connected to the same net as another input. Figure bellow illustrates the case followed by the port map code.Hog_00.PNG

 

    Hog_calc_0_0 : entity work.HogGen
                    port map ( clk    => clk,
                               rst    => rst, 
                               start  => start,
                               down   => Pixel_Block(0,1),
                               left   => Pixel_Block(0,0),
                               right  => Pixel_Block(1,0),
                               top    => Pixel_Block(0,0),
                               Hog    => hog_v(0,0), 
                               done   => done_s(0,0));

I also tried to invert the sequence of port mapping, putting the left input after the top (which is the one that is connectect to the same net) but still the left port was the one connected to ZERO.

Any other suggestion? Thank you for your help.

Eduardo.

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Xilinx Employee
Xilinx Employee
104 Views
Registered: ‎05-14-2008

Re: Input connected to const zero after synthsis

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Have you verified if the post-synthesis netlist functions well by simulation?

This might be due to some cross-boundary optimization as two pins connected/share the same net.

You can try to set -flatten_hierarchy to none, or add "keep_hierarchy" attribute to HogGen module in RTL, and see if this gives different result.

Anyway if the post-synthesis simulation shows good function, this is not an issue.

-vivian

Visitor elrhod
Visitor
88 Views
Registered: ‎03-01-2019

Re: Input connected to const zero after synthsis

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Hi Vivian,

I already have set the  -flatten_hierarchy to none. I will try adding the keep_hierarchy attribute. I am still investigating the post synthesis simulation to understand if it is the case of a  cross-boundary optimization. Will let you know the result as soon as I finish my debug.

Thank you for your suggestions.

Cheers,

Eduardo.

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Xilinx Employee
Xilinx Employee
55 Views
Registered: ‎04-19-2010

Re: Input connected to const zero after synthsis

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You also might want to check and see what is happening inside HogGen.  Without seeing the RTL, I would not know for sure, but I have seen Synthesis connect inputs to 0 based on optimizations inside the driven module.

 

Just a thought.

Visitor elrhod
Visitor
43 Views
Registered: ‎03-01-2019

Re: Input connected to const zero after synthsis

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I have checked and it was a cross-boudary opmisation that connected my input to ZERO.

Thank you for your support.

Regards,

Eduardo.

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