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Observer
Observer
6,613 Views
Registered: ‎10-13-2008

Input <clk> is never used.

Dear all:

      I wrote a example for simple resolution funtion. When it is simulated it shows the following warnings and macro has not created. The warnings were given below.

 

WARNING:Xst:647 - Input <clk> is never used.

WARNING:Xst:647 - Input <a> is never used.
WARNING:Xst:1306 - Output <b> is never assigned.

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

 

entity falling_edgefuntion is
port (clk : in std_logic;
  a : in std_logic;
  b : out std_logic);
   
  
end falling_edgefuntion;

architecture Behavioral of falling_edgefuntion is

function sathish_falling_edge(signal s: std_logic) return boolean is
  begin
   if ((s'event) and (s = '0') and (s'last_value= '1')) then
     return true;
    else
     return false;
    end if;
   end sathish_falling_edge;
begin

   process(clk,a)
   variable c : std_logic;
    begin
     if (sathish_falling_edge(clk)) then
      b <=  a ;
     end if;
      end process;
   
   
end Behavioral;

 

 

Regards,

Sathish Kumar.P

 

 

 

vhdl
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5 Replies
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Explorer
Explorer
6,600 Views
Registered: ‎07-27-2009

Re: Input <clk> is never used.

Hi,

 

Maybe you can try the standard falling_edge function or the more verbose falling_edge(X) == X'event and (X='0'). Your clocked process should only be sensitve to clk.

 

architecture Behavioral of falling_edgefuntion is


begin

   process(clk)

   begin
     if (falling_edge(clk)) then
      b <=  a ;
     end if;
    end process;
   
   
end Behavioral;

 

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Highlighted
Observer
Observer
6,591 Views
Registered: ‎10-13-2008

Re: Input <clk> is never used.

Hi:

        It is the correct falling edge function. while simulation it is working correctly. But during synthesize it shows the following warning. but why i don't know why it is happening. See clk is in the sensitivity list of the process.

 

Regards,

Sathish Kumar.P

 

vhdl
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Highlighted
Teacher
Teacher
6,584 Views
Registered: ‎08-14-2007

Re: Input <clk> is never used.

Hi Sathish,

sensitivity lists are ignored for synthesis anyway.

 

While you can do anything in simulation, synthesis is different.

In the end the synthesis tool tries to identify template patterns and map them to a representation in logic.

I suspect that it just can't handle your function at that place.

Do you see any warnings or infos about ignored statements?

 

Synthesis normally works with either

 

if clk'event and clk='0' then

 

or

 

if falling_edge(clk) then

.

 

The second version uses a function too, but this function is defined in a well known synthesis package.

Maybe you should just use this standard function for a test, to see if everything else is working.

 

Have a nice synthesis

  Eilert

 

 

 

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Highlighted
Observer
Observer
6,584 Views
Registered: ‎10-13-2008

Re: Input <clk> is never used.

Hi eilert :

 

If i kept the function anywhere in the code(package, architecture,entity) it shows the same warning, I want to know how does the synthesis tool identifies the falling edge funtion in the std_logic package  & create the flipflop for falling edge function in rtl schmatics.

where as the code is same as the std_logic why it has not created.

 

Regards,

Sathish Kumar.P

    

vhdl
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Highlighted
Explorer
Explorer
6,574 Views
Registered: ‎07-27-2009

Re: Input <clk> is never used.

Hi sathish,

 

Your code is different from the boiler plate / template synthesis understands. In the end you shouldn't complain about why the synthesis tool doesn't do it the same as your simulation engine but accept the fact that you have to play according to the rules dictated by the synthesis tool.

 

In the synthesis manual you can expect a whole section on what the tool understands. Anything else will probably not work (as you have already found out).

 

Another nice thing is that different synthesis tools support different language constructs, so occasionally you can expect code that works fine in one tool to fail in another.