UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer qiuxiaojie
Observer
8,525 Views
Registered: ‎11-23-2015

Input port not found in the I/O ports list after synthesis

Hello everyone!

 

In this block design,  the input port "GPIO_I [31:0]" is connected to the following IPs:

  1. ZYNQ7 Processing System

  2. speed_switch

  3. sollwert

 

GPIO_I 1.PNG

 

GPIO_I 2.PNG

 

IO Ports.PNG

 

However, after opening the synthesized design and involking I/O ports window, I can't find this input port in the list.

 

Could anybody explain to me:

  1. what the GPIO_I [31:0] port actually is.

  2. why I cannot find this port in the list.  

 

Thanks,

qiuxiaojie

0 Kudos
8 Replies
Explorer
Explorer
8,516 Views
Registered: ‎06-19-2014

Re: Input port not found in the I/O ports list after synthesis

If it is not used in design , it will be removed by synthesis tool. If it is used and you can't find it in netlist after synthesis, the synthesizer may have changed its name or you can track where this signal is going. You may find this bus in some other module which is using it. 

  If you want synthesizer not to remove this signal, you can use 

 

// synthesis attribute keep of GPIO-I is true;

 

in you code.

0 Kudos
Observer qiuxiaojie
Observer
8,501 Views
Registered: ‎11-23-2015

Re: Input port not found in the I/O ports list after synthesis

 

 

 

 

Is my analysis right?

 

 

0 Kudos
Explorer
Explorer
8,498 Views
Registered: ‎06-19-2014

Re: Input port not found in the I/O ports list after synthesis

Yes you are right.

in order to prevent synthesizer from changing signal's name, write following line infront of line where you have declared GPIO_I[31:0] 

 

// synthesis attribute keep of GPIO_I is true;

 

e.g

 

reg [31:0] GPIO_I ;               // synthesis attribute keep of GPIO_I is true;

 

 

0 Kudos
Xilinx Employee
Xilinx Employee
8,495 Views
Registered: ‎07-01-2010

Re: Input port not found in the I/O ports list after synthesis

@qiuxiaojie

 

In order to understand the naming of the ports, did you verify the HDL wrapper created for the bd?

 

To create HDL wrapper right click on BD and select create HDL wrapper.

 

Regards,

Achutha

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------
0 Kudos
Observer qiuxiaojie
Observer
8,486 Views
Registered: ‎11-23-2015

Re: Input port not found in the I/O ports list after synthesis

Hello both of you!

 

I have already created HDL wrapper. Now I post it here.

According to what @a4speaker said, does the code have to be added in front of line 100, i.e. input [31:0]GPIO_I; ?

 

`timescale 1 ps / 1 ps

module system_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
GPIO_I,
GPIO_O,
GPIO_T,
adc_ia_clk_d_o,
adc_ia_clk_o,
adc_ia_dat_d_i,
adc_ia_dat_i,
adc_ib_clk_d_o,
adc_ib_clk_o,
adc_ib_dat_d_i,
adc_ib_dat_i,
adc_it_clk_d_o,
adc_it_clk_o,
adc_it_dat_d_i,
adc_it_dat_i,
adc_vbus_clk_o,
adc_vbus_dat_i,
fmc_m1_en_o,
fmc_m1_fault_i,
gpo_o,
hdmi_data,
hdmi_data_e,
hdmi_hsync,
hdmi_out_clk,
hdmi_vsync,
i2s_bclk,
i2s_lrclk,
i2s_mclk,
i2s_sdata_in,
i2s_sdata_out,
iic_fmc_scl_io,
iic_fmc_sda_io,
iic_mux_scl_I,
iic_mux_scl_O,
iic_mux_scl_T,
iic_mux_sda_I,
iic_mux_sda_O,
iic_mux_sda_T,
muxaddr_out,
otg_vbusoc,
position_i,
pwm_ah_o,
pwm_al_o,
pwm_bh_o,
pwm_bl_o,
pwm_ch_o,
pwm_cl_o,
spdif,
vauxn0,
vauxn8,
vauxp0,
vauxp8,
vn_in,
vp_in);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
input [31:0]GPIO_I;
output [31:0]GPIO_O;
output [31:0]GPIO_T;
output adc_ia_clk_d_o;
output adc_ia_clk_o;
input adc_ia_dat_d_i;
input adc_ia_dat_i;
output adc_ib_clk_d_o;
output adc_ib_clk_o;
input adc_ib_dat_d_i;
input adc_ib_dat_i;
output adc_it_clk_d_o;
output adc_it_clk_o;
input adc_it_dat_d_i;
input adc_it_dat_i;
output adc_vbus_clk_o;
input adc_vbus_dat_i;
output fmc_m1_en_o;
input fmc_m1_fault_i;
output [7:0]gpo_o;
output [15:0]hdmi_data;
output hdmi_data_e;
output hdmi_hsync;
output hdmi_out_clk;
output hdmi_vsync;
output [0:0]i2s_bclk;
output [0:0]i2s_lrclk;
output i2s_mclk;
input i2s_sdata_in;
output [0:0]i2s_sdata_out;
inout iic_fmc_scl_io;
inout iic_fmc_sda_io;
input [1:0]iic_mux_scl_I;
output [1:0]iic_mux_scl_O;
output iic_mux_scl_T;
input [1:0]iic_mux_sda_I;
output [1:0]iic_mux_sda_O;
output iic_mux_sda_T;
output [4:0]muxaddr_out;
input otg_vbusoc;
input [2:0]position_i;
output pwm_ah_o;
output pwm_al_o;
output pwm_bh_o;
output pwm_bl_o;
output pwm_ch_o;
output pwm_cl_o;
output spdif;
input vauxn0;
input vauxn8;
input vauxp0;
input vauxp8;
input vn_in;
input vp_in;

wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire [31:0]GPIO_I;
wire [31:0]GPIO_O;
wire [31:0]GPIO_T;
wire adc_ia_clk_d_o;
wire adc_ia_clk_o;
wire adc_ia_dat_d_i;
wire adc_ia_dat_i;
wire adc_ib_clk_d_o;
wire adc_ib_clk_o;
wire adc_ib_dat_d_i;
wire adc_ib_dat_i;
wire adc_it_clk_d_o;
wire adc_it_clk_o;
wire adc_it_dat_d_i;
wire adc_it_dat_i;
wire adc_vbus_clk_o;
wire adc_vbus_dat_i;
wire fmc_m1_en_o;
wire fmc_m1_fault_i;
wire [7:0]gpo_o;
wire [15:0]hdmi_data;
wire hdmi_data_e;
wire hdmi_hsync;
wire hdmi_out_clk;
wire hdmi_vsync;
wire [0:0]i2s_bclk;
wire [0:0]i2s_lrclk;
wire i2s_mclk;
wire i2s_sdata_in;
wire [0:0]i2s_sdata_out;
wire iic_fmc_scl_i;
wire iic_fmc_scl_io;
wire iic_fmc_scl_o;
wire iic_fmc_scl_t;
wire iic_fmc_sda_i;
wire iic_fmc_sda_io;
wire iic_fmc_sda_o;
wire iic_fmc_sda_t;
wire [1:0]iic_mux_scl_I;
wire [1:0]iic_mux_scl_O;
wire iic_mux_scl_T;
wire [1:0]iic_mux_sda_I;
wire [1:0]iic_mux_sda_O;
wire iic_mux_sda_T;
wire [4:0]muxaddr_out;
wire otg_vbusoc;
wire [2:0]position_i;
wire pwm_ah_o;
wire pwm_al_o;
wire pwm_bh_o;
wire pwm_bl_o;
wire pwm_ch_o;
wire pwm_cl_o;
wire spdif;
wire vauxn0;
wire vauxn8;
wire vauxp0;
wire vauxp8;
wire vn_in;
wire vp_in;

IOBUF iic_fmc_scl_iobuf
(.I(iic_fmc_scl_o),
.IO(iic_fmc_scl_io),
.O(iic_fmc_scl_i),
.T(iic_fmc_scl_t));
IOBUF iic_fmc_sda_iobuf
(.I(iic_fmc_sda_o),
.IO(iic_fmc_sda_io),
.O(iic_fmc_sda_i),
.T(iic_fmc_sda_t));
system system_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.GPIO_I(GPIO_I),
.GPIO_O(GPIO_O),
.GPIO_T(GPIO_T),
.IIC_FMC_scl_i(iic_fmc_scl_i),
.IIC_FMC_scl_o(iic_fmc_scl_o),
.IIC_FMC_scl_t(iic_fmc_scl_t),
.IIC_FMC_sda_i(iic_fmc_sda_i),
.IIC_FMC_sda_o(iic_fmc_sda_o),
.IIC_FMC_sda_t(iic_fmc_sda_t),
.adc_ia_clk_d_o(adc_ia_clk_d_o),
.adc_ia_clk_o(adc_ia_clk_o),
.adc_ia_dat_d_i(adc_ia_dat_d_i),
.adc_ia_dat_i(adc_ia_dat_i),
.adc_ib_clk_d_o(adc_ib_clk_d_o),
.adc_ib_clk_o(adc_ib_clk_o),
.adc_ib_dat_d_i(adc_ib_dat_d_i),
.adc_ib_dat_i(adc_ib_dat_i),
.adc_it_clk_d_o(adc_it_clk_d_o),
.adc_it_clk_o(adc_it_clk_o),
.adc_it_dat_d_i(adc_it_dat_d_i),
.adc_it_dat_i(adc_it_dat_i),
.adc_vbus_clk_o(adc_vbus_clk_o),
.adc_vbus_dat_i(adc_vbus_dat_i),
.fmc_m1_en_o(fmc_m1_en_o),
.fmc_m1_fault_i(fmc_m1_fault_i),
.gpo_o(gpo_o),
.hdmi_data(hdmi_data),
.hdmi_data_e(hdmi_data_e),
.hdmi_hsync(hdmi_hsync),
.hdmi_out_clk(hdmi_out_clk),
.hdmi_vsync(hdmi_vsync),
.i2s_bclk(i2s_bclk),
.i2s_lrclk(i2s_lrclk),
.i2s_mclk(i2s_mclk),
.i2s_sdata_in(i2s_sdata_in),
.i2s_sdata_out(i2s_sdata_out),
.iic_mux_scl_I(iic_mux_scl_I),
.iic_mux_scl_O(iic_mux_scl_O),
.iic_mux_scl_T(iic_mux_scl_T),
.iic_mux_sda_I(iic_mux_sda_I),
.iic_mux_sda_O(iic_mux_sda_O),
.iic_mux_sda_T(iic_mux_sda_T),
.muxaddr_out(muxaddr_out),
.otg_vbusoc(otg_vbusoc),
.position_i(position_i),
.pwm_ah_o(pwm_ah_o),
.pwm_al_o(pwm_al_o),
.pwm_bh_o(pwm_bh_o),
.pwm_bl_o(pwm_bl_o),
.pwm_ch_o(pwm_ch_o),
.pwm_cl_o(pwm_cl_o),
.spdif(spdif),
.vauxn0(vauxn0),
.vauxn8(vauxn8),
.vauxp0(vauxp0),
.vauxp8(vauxp8),
.vn_in(vn_in),
.vp_in(vp_in));
endmodule

0 Kudos
Xilinx Employee
Xilinx Employee
8,307 Views
Registered: ‎07-01-2010

Re: Input port not found in the I/O ports list after synthesis

@qiuxiaojie

 

The behaviour explained indicates some went wrong in the BD generation etc..

Can you share the BD to reproduce the issue?

 

Regards,

Achutha

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------
0 Kudos
Moderator
Moderator
8,304 Views
Registered: ‎01-16-2013

Re: Input port not found in the I/O ports list after synthesis

@qiuxiaojie,

 

Can you Validate the BD and see if there is any error or CW?

Also try to reset the output products and generate them again.

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
0 Kudos
Explorer
Explorer
8,263 Views
Registered: ‎04-28-2015

Re: Input port not found in the I/O ports list after synthesis

Hi,

Were you able to resolve the issue?
If not, please try the above suggestion and let us know if you observe any change.

Thanks,
Tushar.
0 Kudos