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Visitor salamander
Visitor
6,311 Views
Registered: ‎09-13-2007

Insertion of versioning info into VHDL source

I am trying to find a methodology for embedding git versioning in some of my designs. I know how to query git from the command line to pull in the versioning info and if I had the string, I could parse it within VHDL and place it  in internal registers within my design.

 

Any suggestions on how to get the git query into the VHDL source or actually any other suggested means of automatically getting some form of versioning information into my source code  where it can then be encoded into hardware ?

 

 

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Visitor imode69
Visitor
6,301 Views
Registered: ‎08-24-2011

Re: Insertion of versioning info into VHDL source

my advice would be to write a script that wraps git and generates a VHDL ROM with the version info that can be included in your project.  

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Participant jpnaude
Participant
6,285 Views
Registered: ‎03-18-2009

Re: Insertion of versioning info into VHDL source

We do this through the GENERICS parameter of XST. All our designs have versioning generics on their top levels which we overwrite this way. Inside the design we connect the value to a regsiter that we can read when the design is operational in the system.

 

Hope it help,
Jaco

Historian
Historian
6,280 Views
Registered: ‎02-25-2008

Re: Insertion of versioning info into VHDL source


@jpnaude wrote:

We do this through the GENERICS parameter of XST. All our designs have versioning generics on their top levels which we overwrite this way. Inside the design we connect the value to a regsiter that we can read when the design is operational in the system.

 

Hope it help,
Jaco


I do this too. Works like a charm. I generally use generics for the design's assigned part number, released revision, and intermediate build.

 

The original poster mentioned git. If he was using Subversion and TortoiseSVN, the latter has a neat little command-line program that subsitutes things like revision number and date and time for certain macros in the code.

 

 

----------------------------Yes, I do this for a living.
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Scholar markcurry
Scholar
6,276 Views
Registered: ‎09-16-2009

Re: Insertion of versioning info into VHDL source

 

We stick this type of info into a single Block RAM, so it's just a DATA2MEM step to update the info, instead of an entire new implementation (synth/MAP/PAR).

 

--Mark

 

 

 

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Historian
Historian
6,273 Views
Registered: ‎02-25-2008

Re: Insertion of versioning info into VHDL source


@markcurry wrote:

 

We stick this type of info into a single Block RAM, so it's just a DATA2MEM step to update the info, instead of an entire new implementation (synth/MAP/PAR).

 

--Mark 


The usual reason to bump the version number is because the source changed, which means you need to re-synthesize and re-implement anyway.

----------------------------Yes, I do this for a living.
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Scholar markcurry
Scholar
6,271 Views
Registered: ‎09-16-2009

Re: Insertion of versioning info into VHDL source


@bassman59 wrote:
The usual reason to bump the version number is because the source changed, which means you need to re-synthesize and re-implement anyway.

 

Depends - that was originally our thoughts too, and the way we used to do it.  But too many times we ran into cases of mutli-day debug, whirlwind of activity.  Then ready to handoff off to manufacturing and,... "We need you to bump the rev numbers... ". 

 

So, 6-7 hours of rebuild, then retests, etc., etc...

 

Moving it to a RAMB opened up other opportunities.  Engineering does the build, verification etc.  Then "blesses" the FPGA build by modifiying a few bits in that block RAM.  Other info can be stored there as well.

 

Just throwing it out there, as something we've found quite useful.

 

Regards,

 

Mark

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