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Observer
Observer
1,304 Views
Registered: ‎01-23-2017

Is it possible to bind a component instantiated in a dcp after ooc synthesis?

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I'm working with a design flow where a portion (I'll call that the 'module') of the design is synthesized OOC into a DCP. The 'module' instantiates a certain (vhdl) component which is essentially a 'black box' (= not bound to anything) during ooc synthesis because I would like to specify the binding of this black box only later, as part of the complete design:

 

top_level
             [ 'module' DCP   component X ]
                                        |
                                     entity X

I.e., I'd like to give the user (who defines the top_level and other portions of the design) a synthesized DCP of 'module'  but also let them define what entity should be used for component 'X'.

 

Is that possible with Vivado? If so, how?

 

Thanks

- Till

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Observer
Observer
1,593 Views
Registered: ‎01-23-2017

Re: Is it possible to bind a component instantiated in a dcp after ooc synthesis?

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I guess that would work, thanks. However, in our workflow we don't use IPs if not necessary but try to stay with pure vhdl (e.g., I find it cumbersome if I have to customize a certain IP in TCL and then instantiate in vhdl - I'd rather instantiate providing generics to customize a module).

 

In any case, I think I found the solution: in fact, vivado 'just works'. I.e., I can either add sources or even a pre-synthesized DCP of module 'X' to the project and this 'just works'.

 

It turns out that my problems were due to still incomplete or buggy support in vivado (2017.3) for VHDL configurations: I had multiple architectures of module 'X' in my project and wanted to select one by means of a VHDL configuration. It turns out that this does not work properly (yet). So I fell back to selecting the desired architecture from tcl (and not adding any other architectures to the project) thus avoiding VHDL configurations. This solution is less elegant and led to more redundant boilerplate code but it works.

View solution in original post

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Scholar
Scholar
1,207 Views
Registered: ‎06-20-2017

Re: Is it possible to bind a component instantiated in a dcp after ooc synthesis?

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Not what you're looking for, but without time to test possible solutions, a quicker but potentially kludgier way is to just expose the interface to the IP module's top level ports.

Mike
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Moderator
Moderator
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Registered: ‎07-21-2014

Re: Is it possible to bind a component instantiated in a dcp after ooc synthesis?

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@strauman

 

How about using IP-Packager? You can provide the design files to the customer and then custom can add their design files for module X and then package it, then this custom IP can be integrated into the main top-module/design.

 

Thanks,

Anusheel

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Observer
Observer
1,594 Views
Registered: ‎01-23-2017

Re: Is it possible to bind a component instantiated in a dcp after ooc synthesis?

Jump to solution

I guess that would work, thanks. However, in our workflow we don't use IPs if not necessary but try to stay with pure vhdl (e.g., I find it cumbersome if I have to customize a certain IP in TCL and then instantiate in vhdl - I'd rather instantiate providing generics to customize a module).

 

In any case, I think I found the solution: in fact, vivado 'just works'. I.e., I can either add sources or even a pre-synthesized DCP of module 'X' to the project and this 'just works'.

 

It turns out that my problems were due to still incomplete or buggy support in vivado (2017.3) for VHDL configurations: I had multiple architectures of module 'X' in my project and wanted to select one by means of a VHDL configuration. It turns out that this does not work properly (yet). So I fell back to selecting the desired architecture from tcl (and not adding any other architectures to the project) thus avoiding VHDL configurations. This solution is less elegant and led to more redundant boilerplate code but it works.

View solution in original post

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